COMMUNICATION APPARATUS, COMMUNICATION METHOD, AND COMMUNICATION SYSTEM

• US 20100232452A1
• Filed: 05/26/2010
• Published: 09/16/2010
• Est. Priority Date: 01/09/2004
• Status: Active Grant

• Current Assignee: Palmira Wireless AG
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takagi, Masahiro, Utsunomiya, Yoriko, Nishibayashi, Yasuyuki
• Granted Patent: US 8,472,468 B2
• Time in Patent Office: Days
• US Class Current: 370/445
• CPC Class Codes: H04L 1/1607 Details of the supervisory signal
• CPC Class Codes: H04L 1/1614 using bitmaps
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 12/46 Interconnection of networks
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: H04L 2101/622 Layer-2 addresses, e.g. medium access control [MAC] addresses
• CPC Class Codes: H04L 5/0044 allocation of payload
• CPC Class Codes: H04L 5/0055 Physical resource allocation for ACK/NACK for physical mapping arrangements in ARQ protocols H04L1/1861
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04W 28/06 Optimizing the usage of the radio link, e.g. header compression, information sizing , discarding information system modifying transmission characteristic according to link quality by modifying frame length H04L1/0007; dynamic adaptation of the packet size for flow control or congestion control H04L47/365
• CPC Class Codes: H04W 28/065 using assembly or disassembly of packets
• CPC Class Codes: H04W 28/14 using intermediate storage
• CPC Class Codes: H04W 52/0203 in the radio access network or backbone network of wireless communication networks
• CPC Class Codes: H04W 74/0816 with collision avoidance
• CPC Class Codes: H04W 84/12 WLAN [Wireless Local Area Networks]
• CPC Class Codes: Y02B 70/30 Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A physical frame is constructed, the physical frame including a medium access control super-frame payload which in turn includes a plurality of medium access control frames. With respect to the constructed physical frame, virtual carrier sense information is set in the plurality of medium access control frame so that a result of carrier sense is identical to another by virtual carrier sense based on the plurality of medium access control frames in the medium access control super-frame payload. The physical frame in which the virtual carrier sense information has been set is transmitted to a destined communication apparatus.

Claims

1-30. -30. (canceled)

31. A communication circuit used as a component in a communication apparatus, comprising:

a physical frame construction device configured to construct a single physical frame containing a physical header, length information, a first check sequence, and a plurality of MAC frames, the length information representing lengths of the plurality of MAC frames, the first check sequence being for detecting an error which may occur in the length information, each of the plurality of MAC frames including a second check sequence for detecting an error which may occur in each of the plurality of MAC frames; and

a transmission device configured to transmit the physical frame to a destination communication apparatus,

wherein the physical header includes a first header for a first protocol and a second header for a second protocol, the second header following the first header;

the first header is decodable by a first communication apparatus that supports the first protocol and a second communication apparatus that supports the second protocol; and

the second header is decodable by the second communication apparatus.

32. The circuit according to claim 31, further comprising:

a reception device configured to receive an acknowledgement frame as a response to reception of at least one of a plurality of the MAC frames in the physical frame, after the destination communication apparatus receives the physical frame and a Short IFS (SIFS) period elapses.

33. The circuit according to claim 32, further comprising:

a checking device configured to check whether each of the plurality of the MAC frames has been received correctly, based on the acknowledgement frame received by the reception device.

34. The circuit according to claim 32,

wherein sequence numbers are assigned to the MAC frames included in the physical frame, and wherein the acknowledgement frame includes an acknowledgement bit map which includes values of one and zero corresponding to an arrangement of the sequence numbers, the values each indicating whether each of the MAC frames has been received correctly or not.

35. The circuit according to claim 31:

wherein each of the MAC frames further contains a duration field, and values of the duration fields of the MAC frames are identical.

36. The circuit according to claim 31:

wherein the physical frame construction device sets the length information as zero for a MAC frame in the physical frame.

37. A communication apparatus comprising:

an antenna, and

a communication circuit according to claim 31, wherein the transmission device of the communication circuit transmits the physical frame through the antenna to the destination communication apparatus.

48. The circuit according to claim 31, wherein the first header includes information regarding a duration of the physical frame.

49. The circuit according to claim 31:

wherein the first header includes a length field and a rate field; and

wherein a value of the length field divided by a value of the rate field is related to a duration of the physical frame.

50. The circuit according to claim 35:

each value of the duration fields of the MAC frames represents a duration for virtually occupying a communication medium, and the durations represented by the duration fields of the MAC frames are identical.

51. A communication apparatus comprising:

an antenna; and

a communication circuit according to claim 31;

wherein the transmission device of the communication circuit transmits the physical frame through the antenna, and

the reception device of the communication circuit receives the acknowledgement frame through the antenna.

52. The circuit according to claim 31, wherein the circuit is a semiconductor integrated circuit including a CPU that executes a firmware.

38. A communication circuit used as a component in a communication apparatus, comprising:

a physical frame reception device configured to receive a single physical frame containing a physical header, length information, a first check sequence, and a plurality of MAC frames, the length information representing lengths of the plurality of MAC frames, the first check sequence being for detecting an error which may occur in the length information, each of the plurality of MAC frames including a second check sequence for detecting an error which may occur in each of the plurality of MAC frames;

a generation device configured to generate an acknowledgement frame in which MAC frames of the received physical frame are specified to have been received correctly, if no error has been detected on the length information according to the first check sequence and no error has been detected on each of the MAC frames according to the second check sequence corresponding thereto; and

a transmission device configured to transmit the acknowledgement frame as a response to reception of at least one of a plurality of the MAC frames in the physical frame, after the physical frame is received and a Short IFS (SIFS) period elapses,

wherein the physical header includes a first header for a first protocol and a second header for a second protocol, the second header following the first header;

the first header is decodable by a first communication apparatus that supports the first protocol and a second communication apparatus that supports the second protocol; and

the second header is decodable by the second communication apparatus.

39. The circuit according to claim 38, wherein the acknowledgement frame contains a receiving state indicating whether each data frame of the MAC frames included in the physical frame received by the reception device has been received correctly.

40. The circuit according to claim 39:

wherein the physical frame reception device further receives a physical frame retransmitted based on the receiving state, the physical frame including a MAC frame which was not received correctly, and

wherein the transmission device transmits, without referring to a history of past receiving states, a new acknowledgement frame which contains a receiving state indicating only whether a MAC frame included in the retransmitted physical frame has been received correctly.

41. The circuit according to claim 39:

wherein the physical frame reception device further receives a physical frame retransmitted based on the receiving state, the physical frame including a MAC frame which was not received correctly, and

wherein the transmission device transmits a new acknowledgement frame which contains an updated receiving state that is updated from a previous receiving state by a receiving state indicating whether a MAC frame included in the retransmitted physical frame has been received correctly.

42. The circuit according to claim 38,

wherein the plurality of the MAC frames in the physical frame include at least data frames, the physical frame reception device further receives a physical frame retransmitted based on a receiving state, the physical frame including data frames which were not received correctly, and

wherein the construction device constructs a new acknowledgement bit map which is updated from a previous acknowledgement bitmap by one and zero values each indicating whether each of the MAC frames contained in the retransmitted physical frame have been received correctly or not.

43. The circuit according to claim 38:

wherein the plurality of the MAC frames in the physical frame include at least data frames, and

the circuit further comprising;

a buffer configured to temporarily store, of the MAC frames contained in the received physical frame, a MAC frame which has been received correctly, so that the MAC frame can be read out in order of sequence numbers;

wherein the sequence numbers are assigned to the MAC frames included in the physical frame;

a transferring device configured to read from the buffered MAC frames having sequence numbers, and transfer the MAC frames to an upper layer processing, based on a comparison between the sequence numbers of the buffered data frames and sequence numbers of MAC frames contained in a physical frame newly received; and

a deletion device configured to delete the MAC frames transferred from the buffer.

44. The circuit according to claim 38, wherein each of the MAC frames further contains a duration field, and values of the duration fields of the MAC frames are identical.

45. The circuit according to claim 44:

further comprising a recognizing device configured to recognize whether reception or transmission is necessary from any one of the MAC frames correctly received within the physical frame, and when the recognizing device recognizes that reception or transmission is not necessary, a power saving operation is started until end of duration which is set as a value in the duration field of the correctly received MAC frame.

46. The circuit according to claim 38, further comprising:

a physical frame construction device configured to construct another physical frame containing length information and a plurality of MAC frames, the length information of the another physical frame representing lengths of the MAC frames and including a first check sequence, and each of the MAC frames of the another physical frame including a second check sequence,

wherein the plurality of MAC frames within the another physical frame further contain an acknowledgement frame and a plurality of data frames; and

the transmission device transmits the another physical frame without new procedures for contending for a transmission privilege.

47. A communication apparatus comprising:

an antenna, and

a communication circuit according to claim 38, wherein the transmission device of the communication circuit transmits the acknowledgement frame through the antenna.

53. The circuit according to claim 38, wherein the first header includes information regarding a duration of the physical frame.

54. The circuit according to claim 38:

wherein the first header includes a length field and a rate field, and

wherein a value of the length field divided by a value of the rate field is related to a duration of the physical frame.

55. The circuit according to claim 44:

each value of the duration fields of the MAC frames represents a duration for virtually occupying a communication medium, and the durations represented by the duration fields of the MAC frames are identical.

56. A communication apparatus comprising:

an antenna; and

a communication circuit according to claim 38;

wherein the physical frame reception device of the communication circuit, receives the physical frame through the antenna, and

the transmission device of the communication circuit transmits the acknowledgement frame through the antenna.

57. The circuit according to claim 38, wherein the circuit is a semiconductor integrated circuit including a CPU that executes a firmware.