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PATTERN VERIFYING METHOD, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND PATTERN VERIFYING PROGRAM

  • US 20100234973A1
  • Filed: 02/11/2010
  • Published: 09/16/2010
  • Est. Priority Date: 03/11/2009
  • Status: Abandoned Application
First Claim
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1. A pattern verifying method comprising:

  • setting, based on three-dimensional structures of layers of a semiconductor integrated circuit, a specification concerning a layout of a layout pattern arranged on a layer; and

    verifying whether a pattern transferred on a wafer based on design layout data of the layout pattern subjected to proximity correction satisfies the specification.

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