PATTERN VERIFYING METHOD, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND PATTERN VERIFYING PROGRAM

• US 20100234973A1
• Filed: 02/11/2010
• Published: 09/16/2010
• Est. Priority Date: 03/11/2009
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KONOMI, Kenji
• Application Number:
  US12/704,373
• Publication Number:
  US 20100234973A1
• Time in Patent Office: Days
• US Class Current: 700/98
• CPC Class Codes: G03F 1/84 Inspecting
• CPC Class Codes: G03F 7/70441 Optical proximity correction [OPC]
• CPC Class Codes: G03F 7/70616 Monitoring the printed patterns

Abstract

A specification of a layout of a layout pattern arranged on a layer is set based on three-dimensional structures of layers of a semiconductor integrated circuit. It is verified whether a layout pattern formed on a wafer based on design layout data subjected to proximity correction satisfies the specification.

Claims

1. A pattern verifying method comprising:

setting, based on three-dimensional structures of layers of a semiconductor integrated circuit, a specification concerning a layout of a layout pattern arranged on a layer; and

verifying whether a pattern transferred on a wafer based on design layout data of the layout pattern subjected to proximity correction satisfies the specification.

2. The pattern verifying method according to claim 1, wherein the specification concerning the layout is a specification concerning an area of an overlapping section between patterns on the wafer of layers different from each other.

3. The pattern verifying method according to claim 2, wherein the area of the overlapping section between the patterns on the wafer is set based on a function having an amount of an unevenness of the layers as a variable.

4. The pattern verifying method according to claim 2, wherein the area of the overlapping section between the patterns on the wafer is set based on a function having a tilt of the layers as a variable.

5. The pattern verifying method according to claim 1, wherein, in the proximity correction, correction of the design layout data is performed such that, when photolithography is performed with exposure conditions fixed to best conditions, a dimension difference between a pattern on the wafer obtained by the photolithography and the pattern on the wafer obtained from the design layout data is minimized.

6. The pattern verifying method according to claim 1, wherein the verifying whether the pattern on the wafer satisfies the specification includes determining whether the pattern on the wafer transferred through photolithography process satisfies the specification even if photolithography condition including an exposure dose or a focus position in the photolithography process is varied.

7. The pattern verifying method according to claim 1, further comprising performing the proximity correction again when it is determined in the verification that the pattern on the wafer does not satisfy the specification.

8. The pattern verifying method according to claim 1, further comprising correcting the design layout data when it is determined in the verification that the pattern on the wafer does not satisfy the specification.

9. The pattern verifying method according to claim 1, further comprising changing a process condition when it is determined in the verification that the pattern on the wafer does not satisfy the specification.

10. The pattern verifying method according to claim 1, wherein the specification is set by using dimension information of the three-dimensional structures and characteristic values of materials of the layers of the semiconductor integrated circuit.

11. The pattern verifying method according to claim 1, wherein the specification is set by using functions of dimension information of the three-dimensional structures and characteristic values of the materials of the layers of the semiconductor integrated circuit.

12. A method of manufacturing a semiconductor device comprising:

setting, based on three-dimensional structures of layers of a semiconductor integrated circuit, a specification concerning a layout of a layout pattern arranged on a layer;

verifying whether a pattern transferred on a wafer based on design layout data subjected to proximity correction satisfies the specification; and

transferring a pattern onto a semiconductor substrate based on the design layout verified as satisfying the specification.

13. The method of manufacturing a semiconductor device according to claim 12, wherein the specification concerning the layout is a specification concerning an area of an overlapping section between the pattern on a wafer which is an impurity diffusing layer of a first layer and the pattern on a wafer which is a contact electrode of a second layer.

14. The method of manufacturing a semiconductor device according to claim 13, wherein the area of the overlapping section between the patterns on the wafer is set based on a function having an amount of an unevenness of the impurity diffusing layer as a variable.

15. The method of manufacturing a semiconductor device according to claim 14, wherein, when the an amount of an unevenness of the impurity diffusing layer is represented as h, a function having h as a variable is represented as f(h), and a contact area on a plane between the impurity diffusing layer and the contact electrode is represented S, a specification SP concerning an area of an overlapping section between the impurity diffusing layer and the contact electrode is given by SP=S+f(h).

16. The method of manufacturing a semiconductor device according to claim 12, wherein the specification concerning the layout is a specification concerning an area of an overlapping section between the pattern on a wafer of a selective epitaxial layer of a first layer and the pattern on a wafer of a contact electrode of a second layer.

17. The method of manufacturing a semiconductor device according to claim 16, wherein the area of the overlapping section between the patterns on a wafer is set based on a function having a tilt angle of the selective epitaxial layer as a variable.

18. The method of manufacturing a semiconductor device according to claim 17, wherein, when a tilt angle of the selective epitaxial layer is represented as θ

and a contact area on a plane between the selective epitaxial layer and the contact electrode is represented as S, a specification SP concerning an area of an overlapping section between the selective epitaxial layer and the contact electrode is given by SP=S/cos θ

.

19. A pattern verifying computer program product for causing a computer to execute:

verifying whether a pattern transferred on a wafer based on a design layout data subjected to proximity correction satisfies a specification concerning a layout of a layout pattern set based on three-dimensional structures of layers of a semiconductor integrated circuit.

20. The pattern verifying program product according to claim 19, wherein the specification concerning the layout is a specification concerning an area of an overlapping section between the patterns on the wafer of layers.