VICTIM CACHE LATERAL CASTOUT TARGETING

• US 20100235577A1
• Filed: 12/19/2008
• Published: 09/16/2010
• Est. Priority Date: 12/19/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Starke, William J., Williams, Derek E., Siegel, Michael S., Guthrie, Guy L.
• Granted Patent: US 8,489,819 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning

Abstract

A data processing system includes a plurality of processing units coupled by an interconnect fabric. In response to a data request, a victim cache line is selected for castout from a first lower level cache of a first processing unit, and a target lower level cache of one of the plurality of processing units is selected based upon architectural proximity of the target lower level cache to a home system memory to which the address of the victim cache line is assigned. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that the target lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.

Claims

1. A method of data processing in a data processing system including a plurality of processing units including a first processing unit and a second processing unit coupled by an interconnect fabric, wherein the first processing unit has a first processor core and associated first upper and first lower level caches and the second processing unit has a second processor core and associated second upper and lower level caches, said method comprising:

in response to a data request, selecting a victim cache line to be castout from the first lower level cache;

selecting a target lower level cache of one of the plurality of processing units based upon architectural proximity of the target lower level cache to a home system memory to which an address of the victim cache line is assigned;

the first processing unit issuing a lateral castout (LCO) command on the interconnect fabric, wherein the LCO command identifies the victim cache line to be castout from the first lower level cache and indicates that the target lower level cache is an intended destination of the victim cache line; and

in response to a coherence response to the LCO command indicating success of the LCO command, removing the victim cache line from the first lower level cache and holding the victim cache line in the second lower level cache.

2. The method of claim 1, wherein the first and second lower level caches are victim caches.

3. The method of claim 1, wherein:

the victim cache line is a first victim cache line; and

the method further comprises evicting a second victim cache line from the second lower level cache to make room for the first victim cache line in the second lower level cache.

4. The method of claim 1, wherein said lateral castout command identifies the second lower level cache as the target lower level cache.

5. The method of claim 1, and further comprising:

in response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit transmitting the victim cache line to the second lower level cache.

6. The method of claim 1, wherein selecting a target lower level cache comprises:

determining a pool containing multiple lower level caches architecturally proximate to the home system memory; and

selecting the target lower level cache from the pool.

7. The method of claim 1, wherein selecting a target lower level cache comprises:

selecting the target lower level cache utilizing a base address register facility.

8. A data processing system, comprising:

an interconnect fabric;

a plurality of processing units coupled to the interconnect fabric, the plurality of processing units including a first processing unit and a second processing unit, wherein the first processing unit has a first processor core and associated first upper and first lower level caches, and wherein the second processing unit has a second processor core and associated second upper and lower level caches; and

a home system memory coupled to the interconnect fabric, wherein the home system memory is assigned a plurality of addresses including an address;

wherein the first processing unit, in response to a data request, selects a victim cache line associated with the address to be castout from the first lower level cache, selects a target lower level cache of one of the plurality of processing units based upon architectural proximity of the target lower level cache to the home system memory to which the address of the victim cache line is assigned, and issues a lateral castout (LCO) command on the interconnect fabric, the LCO command identifying the victim cache line to be castout from the first lower level cache and indicating that the target lower level cache is an intended destination of the victim cache line; and

wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from the first lower level cache and the second lower level cache holds the victim cache line.

9. The data processing system of claim 8, wherein the first and second lower level caches are victim caches.

10. The data processing system of claim 8, wherein:

the victim cache line is a first victim cache line; and

the second lower level cache evicts a second victim cache line to make room for the first victim cache line in the second lower level cache.

11. The data processing system of claim 8, wherein said lateral castout command identifies the second lower level cache as the target lower level cache.

12. The data processing system of claim 8, wherein the first processing unit transmits the victim cache line to the second lower level cache in response to a coherence response to the LCO command indicating success of the LCO command.

13. The data processing system of claim 8, wherein the first processing unit selects the target lower level cache by determining a pool containing multiple lower level caches architecturally proximate to the home system memory and selecting the target lower level cache from the pool.

14. The data processing system of claim 8, wherein the first processing unit includes a base address register facility and select the target lower level cache utilizing the base address register facility.

15. A processing unit for a data processing system including a home system memory and a plurality of processing units coupled by an interconnect fabric, wherein the home system memory is assigned a plurality of addresses including an address, the processing unit comprising:

the processing unit has a first processor core and associated first upper and first lower level caches;

wherein the processing unit, in response to a data request, selects a victim cache line associated with the address to be castout from the first lower level cache, selects a target lower level cache of one of the plurality of processing units based upon architectural proximity of the target lower level cache to the home system memory to which the address of the victim cache line is assigned, and issues a lateral castout (LCO) command on the interconnect fabric, the LCO command identifying the victim cache line to be castout from the first lower level cache and indicating that the target lower level cache is an intended destination of the victim cache line; and

wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from the first lower level cache for storage in a second lower level cache.

16. The processing unit of claim 15, wherein the first and second lower level caches are victim caches.

17. The processing unit of claim 15, wherein said lateral castout command identifies the second lower level cache as the target lower level cache.

18. The processing unit of claim 15, wherein the first processing unit transmits the victim cache line to the second lower level cache in response to a coherence response to the LCO command indicating success of the LCO command.

19. The processing unit of claim 15, wherein the processing unit selects the target lower level cache by determining a pool containing multiple lower level caches of the data processing system that are architecturally proximate to the home system memory and selecting the target lower level cache from the pool.

20. The processing system of claim 15, wherein the processing unit includes a base address register facility and select the target lower level cache utilizing the base address register facility.