Multi-Domain Management of a Cache in a Processor System

• US 20100235580A1
• Filed: 04/06/2009
• Published: 09/16/2010
• Est. Priority Date: 03/11/2009
• Status: Active Grant

• Current Assignee: MACOM Connectivity Solutions, LLC (MACOM Technology Solutions Holdings, Inc.)
• Original Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Bouvier, Daniel
• Granted Patent: US 8,176,282 B2
• Time in Patent Office: Days
• US Class Current: 711/129
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455

Abstract

A system and method are provided for managing cache memory in a computer system. A cache controller portions a cache memory into a plurality of partitions, where each partition includes a plurality of physical cache addresses. Then, the method accepts a memory access message from the processor. The memory access message includes an address in physical memory and a domain identification (ID). A determination is made if the address in physical memory is cacheable. If cacheable, the domain ID is cross-referenced to a cache partition identified by partition bits. An index is derived from the physical memory address, and a partition index is created by combining the partition bits with the index. A processor is granted access (read or write) to an address in cache defined by partition index.

Claims

1. A computer system for managing a cache memory, the system comprising:

a processor having an address interface for sending a memory access message including an address in physical memory and a domain identification (ID);

a cache memory portioned into a plurality of partitions, where each partition includes a plurality of physical cache addresses;

a cache controller having an interface to accept the memory access message from the processor, the cache controller determining if the address in physical memory is cacheable, and if cacheable, cross-referencing the domain ID to a cache partition identified by partition bits, deriving an index from the physical memory address, creating a partition index by combining the partition bits with the index, and granting the processor access to an address in cache defined by partition index.

2. The system of claim 1 wherein the cache controller accepts a memory access message with an address in physical memory and a domain ID, and if the domain ID is not recognized, performs an operation selected from a group consisting of ignoring the memory access message, cross-referencing the domain ID to a default cache partition, and originating a processor machine check error message.

3. The system of claim 1 wherein the cache controller sequentially accepts a first memory access message with a first address in physical memory and a first domain ID, and a second memory access message with a second address in physical memory and a second domain ID, the cache controller cross-referencing the first and second domain IDs to a shared first cache partition, and granting access to the first and second cache addresses in the first cache partition.

4. The system of claim 1 further comprising:

a plurality of applications, each enabled as processor readable code; and

,

wherein the processor includes a memory map unit (MMU) with a page table map of virtual memory addresses for each application cross-referenced to addresses in the physical memory, and the domain ID associated with each address in physical memory, and where each application is assigned a unique domain ID.

5. The system of claim 4 wherein the cache controller sequentially accepts memory access messages associated with each application, cross-references domain IDs to cache partitions, and grants each application access to addresses in a corresponding cache partition.

6. The system of claim 1 further comprising:

a plurality of processors, each processor including an MMU, the plurality including at least two heterogeneous processors having different MMU algorithms for associating virtual addresses to addresses in physical memory;

wherein each MMU includes a page table map of virtual memory addresses cross-referenced to addresses in the physical memory identified, and where each heterogeneous processor is associated with a unique domain ID; and

,

wherein the cache memory includes a cache partition associated with each of the heterogeneous processors.

7. The system of claim 1 further comprising:

a plurality of OSs enabled as computer readable code;

wherein the processor includes an MMU with a page table map of virtual addresses cross-referenced to addresses in the physical memory, where each OS is associated with a unique domain ID;

wherein the processor receives requests to access virtual memory addresses from the plurality of OSs, accesses the MMU to recover cross-referenced addresses in physical memory and associated domain IDs, and sends the addresses in physical memory and domain IDs to the cache controller as memory access messages; and

,

wherein the cache memory includes a cache partition associated with each OS.

8. The system of claim 1 further comprising:

a plurality of homogeneous processors;

wherein each processor including an MMU with a page table map of virtual addresses cross-referenced to addresses in the physical memory, where each homogeneous processor is associated with a unique domain ID;

wherein each homogeneous processor receives a request to access virtual memory addresses from a corresponding OS, accesses its corresponding MMU to recover cross-referenced addresses in physical memory and associated domain IDs, and sends the addresses in physical memory and domain IDs to the cache controller as memory access messages; and

,

wherein the cache memory includes a cache partition associated with each homogeneous processor.

9. The system of claim 1 further comprising:

an OS enabled as computer readable code;

wherein the processor includes an MMU with a page table map of virtual memory addresses cross-referenced to addresses in the physical memory identified with a domain ID; and

,

wherein the OS is assigned addresses in a physical memory domain at initialization, builds the page table map, and loads the page table map into the MMU; and

,

wherein the cache controller builds a partition list cross-referencing domain IDs to partition bits at initialization.

10. The system of claim 1 further comprising:

a plurality of OSs enabled as processor readable code;

a first subsystem including a plurality of symmetric processors, each symmetric processor including an MMU;

a second subsystem including a plurality asymmetric processors, each asymmetric processor including an MMU;

wherein each MMU includes a map of virtual memory addresses cross-referenced to addresses in the physical memory identified, where each processor in the first and second subsystems is associated with a unique domain ID;

wherein each processor from the first and second subsystems receives requests to access virtual memory locations from an OS, accesses its MMU to recover cross-referenced addresses in physical memory and associated domain IDs, and sends the addresses in physical memory and domain IDs to the cache controller as memory access messages; and

,

wherein the cache memory includes a cache partition associated with each processor in the first and second subsystems.

11. The system of claim 1 further comprising:

a plurality of processors including a first, second, and third processor, each including an MMU;

wherein the MMUs for the first and second processors include a map of virtual memory addresses cross-referenced to addresses in the physical memory identified with a shared first domain ID, not shared with the third processor; and

,

wherein the cache controller receives a memory access message with an address in physical memory and the first domain ID from the first processor, the cache controller determining if the first domain ID is shared with another processor, and since it is shared, sending a notification message to the second processor, but not the third processor, that data in a shared cache partition is being accessed.

12. In a computer system, a method for managing a cache memory, the method comprising:

a cache controller portioning a cache memory into a plurality of partitions, where each partition includes a plurality of physical cache addresses;

accepting a memory access message from the processor, the memory access message including an address in physical memory and a domain identification (ID);

determining if the address in physical memory is cacheable;

if cacheable, cross-referencing the domain ID to a cache partition identified by partition bits;

deriving an index from the physical memory address;

creating a partition index by combining the partition bits with the index; and

,

granting a processor access to an address in cache defined by partition index.

13. The method of claim 12 wherein determining if the address in physical memory is cacheable includes failing to recognize a domain ID associated with an accepted memory access message;

and,

the method further comprising;

performing an operation selected from a group consisting of ignoring the memory access message, cross-referencing the domain ID to a default cache partition, and originating a processor machine check error message.

14. The method of claim 12 wherein accepting the memory access message includes sequentially accepting a first memory access message with a first address in physical memory and a first domain ID, and a second memory access message with a second address in physical memory and a second domain ID;

wherein cross-referencing the domain ID to the cache partition identified by partition bits includes cross-referencing the first and second domain IDs to a shared first cache partition; and

,

wherein granting the processor access to the address in cache defined by partition index includes granting access to the first and second cache addresses in the first cache partition.

15. The method of claim 12 further comprising:

generating a memory map unit (MMU) with a page table map of virtual memory addresses for a plurality of applications enabled as computer readable code cross-referenced to addresses in the physical memory; and

,

associating a domain ID with each address in physical memory, where each application is assigned a unique domain ID.

16. The method of claim 15 wherein accepting the memory access message includes sequentially accepting memory access messages associated with each application;

and,

wherein cross-referencing the domain ID to the cache partition includes cross-referencing domain IDs associated with each application to a corresponding cache partition.

17. The method of claim 12 further comprising:

generating a plurality of MMUs for a corresponding plurality of processors, including at least two heterogeneous processors having different MMU algorithms for associating virtual addresses to addresses in physical memory, where each MMU includes a table map of virtual memory addresses cross-referenced to addresses in physical memory;

associating a domain ID with each heterogeneous processor; and

,

wherein cross-referencing the domain ID to the cache partition includes cross-referencing the domain IDs of each heterogeneous processor to a unique cache partition.

18. The method of claim 12 further comprising:

generating a memory map unit (MMU) with a page table map of virtual memory addresses for a plurality of operating systems (OSs) enabled as computer readable code cross-referenced to addresses in the physical memory; and

,

associating a domain ID with each address in physical memory, where each OS is assigned a unique domain ID.

19. The method of claim 18 further comprising:

generating a plurality of MMUs for a corresponding plurality of processors, including at least two homogeneous processors, where each processor and MMU are associated with a corresponding OS, and each MMU includes a table map of virtual memory addresses cross-referenced to addresses in the physical memory;

associating a unique domain ID with each OS; and

,

wherein cross-referencing the domain ID to the cache partition includes cross-referencing the domain IDs of each OS to a unique cache partition.

20. The method of claim 12 further comprising:

assigning an OS, enabled as computer readable code, addresses in a physical memory domain at initialization; and

,

wherein portioning the cache memory into a plurality of partitions includes building a partition list cross-referencing domain IDs to partition bits at initialization.

21. The method of claim 12 further comprising:

generating a plurality of MMUs for a corresponding plurality of processors, including a first subsystem including a plurality of symmetric processors, and a second subsystem including a plurality of asymmetric processors, where each MMU includes a table map of virtual memory addresses cross-referenced to addresses in the physical memory;

associating a unique domain ID to each processor;

wherein accepting the memory access message includes sequentially accepting memory access messages from processors in the first and second subsystems; and

,

wherein cross-referencing the domain ID to the cache partition includes cross-referencing the domain IDs of each processor in the first and second subsystems to a unique cache partition.

22. The method of claim 12 further comprising:

generating a plurality of MMUs for a corresponding plurality of processors, including a first MMU for a first processor, a second MMU for a second processor, and a third MMU for a third processor, where each MMU includes a table map of virtual memory addresses cross-referenced to addresses in the physical memory;

associating a shared first domain ID to the first and second processors, but not the third processor;

wherein accepting the memory access message includes accepting a memory access message from the first processor with the first domain ID;

wherein cross-referencing the domain ID to the cache partition includes;

determining if the first domain ID is shared with another processor, and since it is shared;

sending a notification message to the second processor, but not the third processor, that data in a shared cache partition is being accessed.