Lateral Castout (LCO) Of Victim Cache Line In Data-Invalid State

• US 20100235584A1
• Filed: 03/11/2009
• Published: 09/16/2010
• Est. Priority Date: 03/11/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Le, Hien M., Williams, Derek E., Siegel, Michael S., Guthrie, Guy L., Williams, Phillip G., Ng, Alvan W.
• Granted Patent: US 8,949,540 B2
• Time in Patent Office: Days
• US Class Current: 711/135
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel

Abstract

A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect fabric a lateral castout (LCO) command identifying the victim cache line to be castout from the first lower level cache, indicating the data-invalid coherence state, and indicating that a lower level cache is an intended destination of the victim cache line. In response to a coherence response to the LCO command indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in a second lower level cache of a second processing unit in the data-invalid coherence state.

Claims

1. A method of data processing in a data processing system including a plurality of processing units including a first processing unit and a second processing unit coupled by an interconnect fabric, wherein the first processing unit has a first processor core having an associated first upper level cache and a first lower level cache, and wherein the second processing unit has a second processor core and an associated second upper level cache and second lower level cache, said method comprising:

selecting a victim cache line to be castout from the first lower level cache, wherein the victim cache line has a data-invalid coherence state;

the first processing unit issuing a lateral castout (LCO) command on the interconnect fabric, wherein the LCO command identifies the victim cache line to be castout from the first lower level cache, indicates the data-invalid coherence state, and indicates that a lower level cache is an intended destination of the victim cache line; and

in response to a coherence response to the LCO command indicating success of the LCO command, removing the victim cache line from the first lower level cache and holding the victim cache line in the second lower level cache in the data-invalid coherence state.

2. The method of claim 1, wherein the first and second lower level caches are victim caches, and wherein the first processing unit performs the selecting and removing steps.

3. The method of claim 1, wherein the selecting includes:

determining membership of each of a plurality of cache lines within a congruence class in either a first class or a second class; and

selecting as the victim cache line one of one or more cache lines in the second class.

4. The method of claim 3, and further comprising maintaining in the first class one or more cache lines of the congruence class more likely to be accessed by the first processor core.

5. The method of claim 1, wherein:

the victim cache line is a first victim cache line; and

the method further comprises evicting a second victim cache line from the second lower level cache to make room for the first victim cache line in the second lower level cache.

6. The method of claim 1, wherein said lateral castout command identifies the second lower level cache as the destination.

7. The method of claim 1, wherein:

the plurality of processing units are grouped in at least a first coherence domain including the first processing unit and a second coherence domain; and

the data-invalid coherence state indicates that a valid copy of the victim cache line was sourced to a processing unit among the plurality of processing units belonging to the second coherence domain.

8. A data processing system, comprising:

an interconnect fabric; and

a plurality of processing units coupled to the interconnect fabric, the plurality of processing units including a first processing unit and a second processing unit, wherein the first processing unit has a first processor core and associated first upper and first lower level caches, and wherein the second processing unit has a second processor core and associated second upper and lower level caches;

wherein the first processing unit selects a victim cache line to be castout from the first lower level cache and issues a lateral castout (LCO) command on the interconnect fabric, the LCO command identifying the victim cache line to be castout from the first lower level cache, indicates the data-invalid coherence state, and indicates that a lower level cache is an intended destination of the victim cache line; and

wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from the first lower level cache and the second lower level cache holds the victim cache line in the data-invalid coherence state.

9. The data processing system of claim 8, wherein the first and second lower level caches are victim caches.

10. The data processing system of claim 8, wherein the first processing unit selects the victim cache line by determining membership of each of a plurality of cache lines of the first lower level cache within a congruence class in either a first class or a second class and selects as the victim cache line one of one or more cache lines in the second class.

11. The data processing system of claim 10, wherein the first lower level cache maintains in the first class one or more cache lines of the congruence class more likely to be accessed by the first processor core.

12. The data processing system of claim 8, wherein:

the victim cache line is a first victim cache line; and

the method further comprises evicting a second victim cache line from the second lower level cache to make room for the first victim cache line in the second lower level cache.

13. The data processing system of claim 8, wherein said lateral castout command identifies the second lower level cache as the destination.

14. The data processing system of claim 8, wherein:

the plurality of processing units are grouped in at least a first coherence domain including the first processing unit and a second coherence domain; and

the data-invalid coherence state indicates that a valid copy of the victim cache line was sourced to a processing unit among the plurality of processing units belonging to the second coherence domain.

15. A processing unit for a data processing system including a plurality of processing units coupled by an interconnect fabric, the processing unit comprising:

the processing unit has a first processor core and associated first upper and first lower level caches;

wherein the processing unit, in response to a data request, selects a victim cache line to be castout from the first lower level cache and issues a lateral castout (LCO) command on the interconnect fabric, the LCO command identifying the victim cache line to be castout from the first lower level cache, indicates the data-invalid coherence state, and indicates that a lower level cache is an intended destination of the victim cache line; and

wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from the first lower level cache for storage in a second lower level cache in the data-invalid coherence state.

16. The processing unit of claim 15, wherein:

the first lower level cache is a victim cache; and

the processing unit is a single integrated circuit chip.

17. The processing unit of claim 15, wherein the processing unit selects the victim cache line by determining membership of each of a plurality of cache lines within a congruence class in either a first class or a second class and by selecting as the victim cache line one of one or more cache lines received in the second class.

18. The processing unit of claim 17, wherein the processing unit maintains in the first class one or more cache lines of the congruence class more likely to be accessed by the first processor core.

19. The processing unit of claim 15, wherein said lateral castout command identifies the second lower level cache as the destination.

20. The processing unit of claim 15, wherein:

the plurality of processing units are grouped in at least a first coherence domain including the first processing unit and a second coherence domain; and

the data-invalid coherence state indicates that a valid copy of the victim cache line was sourced to a processing unit among the plurality of processing units belonging to the second coherence domain.