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MULTI-CORE PROCESSOR SNOOP FILTERING

  • US 20100235586A1
  • Filed: 03/11/2009
  • Published: 09/16/2010
  • Est. Priority Date: 03/11/2009
  • Status: Active Grant
First Claim
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1. A central processing unit comprising:

  • a plurality of processor packages, each processor package including at least one processor core, each processor core having respective cache memory management hardware comprising;

    a cache memory device configured to store cache lines for use by the processor core, wherein each cache line corresponds to a portion of a page of memory;

    a page status table configured to store page status information, wherein the page status information indicates whether any portion of a page of memory corresponding to a cache line stored in the cache memory device is shared by another processor core from the same one of the plurality of processor packages and whether any portion of the page of memory corresponding to the cache line is shared by another processor core in a different one of the plurality of processor packages; and

    a cache controller configured to determine, upon a cache miss, whether to broadcast a snoop request to any other processor cores based at least in part on the page status information stored in the page status table.

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