MULTI-CORE PROCESSOR SNOOP FILTERING

• US 20100235586A1
• Filed: 03/11/2009
• Published: 09/16/2010
• Est. Priority Date: 03/11/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Gonion, Jeffry
• Granted Patent: US 8,868,847 B2
• Time in Patent Office: Days
• US Class Current: 711/144
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems, methods, and devices for reducing snoop traffic in a central processing unit are provided. In accordance with one embodiment, an electronic device includes a central processing unit having a plurality of cores. A cache memory management system may be associated with each core that includes a cache memory device configured to store a plurality of cache lines, a page status table configured to track pages of memory stored in the cache memory device and to indicate a status of each of the tracked pages of memory, and a cache controller configured to determine, upon a cache miss, whether to broadcast a snoop request based at least in part on the status of one of the tracked pages in the page status table.

Claims

1. A central processing unit comprising:

a plurality of processor packages, each processor package including at least one processor core, each processor core having respective cache memory management hardware comprising;

a cache memory device configured to store cache lines for use by the processor core, wherein each cache line corresponds to a portion of a page of memory;

a page status table configured to store page status information, wherein the page status information indicates whether any portion of a page of memory corresponding to a cache line stored in the cache memory device is shared by another processor core from the same one of the plurality of processor packages and whether any portion of the page of memory corresponding to the cache line is shared by another processor core in a different one of the plurality of processor packages; and

a cache controller configured to determine, upon a cache miss, whether to broadcast a snoop request to any other processor cores based at least in part on the page status information stored in the page status table.

2. The central processing unit of claim 1, wherein the cache controller of each cache memory management hardware is configured, upon a cache miss, to broadcast a snoop request to all other processor cores when the page status information indicates that any portion of the page to which a cache line of the cache miss corresponds is shared by a processor core from another one of the plurality of processor packages.

3. The central processing unit of claim 1, wherein the cache controller of each cache memory management hardware is configured, upon a cache miss, to broadcast a snoop request only to other processor cores in the same one of the plurality of processor packages when the page status information indicates that any portion of the page to which a cache line of the cache miss corresponds is shared by a processor core from the same one of the plurality of processor packages but not shared by a processor core from a different one of the plurality of processor packages.

4. The central processing unit of claim 1, wherein the cache controller of each cache memory management hardware is configured, upon a cache miss, to access a cache line from main memory without broadcasting a snoop request when the page status information indicates that no portion of the page to which the cache line of the cache miss corresponds is shared by any other processor cores.

5. The central processing unit of claim 1, wherein the page status table of each cache memory management hardware is configured, upon receipt of a snoop request regarding a page to which a cache line stored in the cache memory device belongs, to store page status information indicating that a portion of the page is shared when such page status information is not stored in the page status table.

6. The central processing unit of claim 1, wherein the page status table of each cache memory management hardware is configured, upon receipt of a snoop request regarding a page to which a cache line not stored in the cache memory device belongs, to clear page status information indicating that a portion of the page is shared when such information is stored in the page status table.

7. An electronic device comprising:

a central processing unit having a plurality of cores, wherein a cache memory management system is associated with each of the plurality of cores, the cache memory management system comprising;

a cache memory device configured to store a plurality of cache lines, wherein each of the plurality of cache lines corresponds respectively to one of a plurality of lines of one of a plurality of pages of memory;

a page status table configured to track a subset of pages of memory stored in the cache memory device and to indicate a status of each tracked page, wherein the status of each tracked page indicates which other cores of the plurality of cores are currently using at least one of the plurality of lines of the tracked page; and

a cache controller configured to determine, upon a cache miss, whether to broadcast a snoop request to another cache controller associated with any other of the plurality of cores based at least in part on the status of one of the tracked pages when a missed cache line corresponds to one of the plurality of lines of the one of the tracked pages.

8. The device of claim 7, wherein the subset of pages tracked by each page status table comprises all pages corresponding to the plurality of cache lines stored in the respective cache memory device.

9. The device of claim 7, wherein the subset of pages tracked by each page status table comprises fewer than all pages corresponding to the plurality of cache lines stored in the respective cache memory device.

10. The device of claim 9, wherein the subset of pages corresponding to the plurality of cache lines comprises a predetermined number of pages corresponding to most recently accessed cache lines.

11. The device of claim 7, wherein each page status table is configured to track one of the plurality of pages of memory stored in the memory device when, upon a cache miss, a missed cache line does not correspond to one of the plurality of lines of one of the tracked pages.

12. The device of claim 7, wherein each page status table is configured to not track one of the plurality of pages of memory stored in the memory device when none of the cache lines stored in the respective cache memory device corresponds to one of the plurality of lines of the one of the tracked pages.

13. The device of claim 7, wherein each page status table is configured not to track one of the plurality of pages of memory stored in the memory device when, upon receipt of a snoop request from a cache controller associated with another of the plurality of cores for a line corresponding to one of the plurality of lines of the one of the tracked pages, none of the cache lines stored in the respective cache memory device corresponds to one of the plurality of lines of the one of the tracked pages.

14. The device of claim 7, wherein the cache controller is configured to broadcast a request only to other cores of the plurality of cores that the page status table indicates are currently using one of the plurality of lines of one of the tracked pages.

15. The electronic device of claim 7, wherein the electronic device comprises a notebook computer, a desktop computer, a handheld computer, a portable phone, or any combination thereof.

16. A method comprising:

tracking, from a processor of a first processor package of a central processing unit having a plurality of processor packages, wherein each of the plurality of processor packages includes a plurality of processors, whether any line of a page of main memory is shared by another processor of the first processor package and whether any line of the page of memory is shared by a processor of another processor package; and

determining, upon a cache miss in the first processor for a line of memory of the page of main memory, whether to broadcast a snoop request to any other processors based at least in part on whether any line of the page of main memory is shared by another processor of the first processor package or by a processor of another processor package.

17. The method of claim 16, comprising determining, upon the cache miss in the first processor for the line of memory of the page of main memory, to broadcast a snoop request to all other processors of the central processing unit any line of the page of main memory is shared by a processor of another processor package.

18. The method of claim 16, comprising determining, upon the cache miss in the first processor for the line of memory of the page of main memory, to broadcast a snoop request only to other processors of the first processor package when any line of the page of main memory is shared by another processor of the first processor package but not by a processor of another processor package.

19. The method of claim 16, comprising determining, upon the cache miss in the first processor for the line of memory of the page of main memory, not to broadcast a snoop request when no lines of the page of main memory are shared by another processor of the first processor package or by a processor of another processor package.

20. The method of claim 16, comprising tracking, from the processor of the first processor package, whether any line of any page of main memory that is being used by the processor of the first processor package is shared by another processor of the first processor package and whether any line of any page of main memory that is being used by the processor of the first processor package is shared by a processor of another processor package.

21. The method of claim 16, comprising tracking, from the processor of the first processor package, whether any line of any page in a predetermined number of pages of main memory most recently accessed by the processor of the first processor package is shared by another processor of the first processor package and whether any line of any page in a predetermined number of pages of main memory most recently accessed by the processor of the first processor package is shared by a processor of another processor package.

22. An electronic device comprising:

a memory device configured to store physically-addressed pages; and

a central processing unit having a plurality of cores, wherein a cache memory management system is associated with each of the plurality of cores, the cache memory management system comprising;

a translation lookaside buffer configured to map a plurality of virtually-addressed pages to a respective plurality of the physically-addressed pages;

a cache memory device configured to store cache lines corresponding to one or more of the plurality of the physically-addressed pages;

a page status table configured to store data indicating whether at least one other cache memory management system of the central processing unit is currently storing a cache line corresponding to one of a subset of the plurality of the physically-addressed pages; and

a cache controller configured to determine, upon a cache miss, whether to broadcast a snoop request to another cache memory management system based at least in part on the data stored in the page status table;

wherein the central processing unit is configured to run an operating system kernel, wherein the operating system kernel is configured to communicate to each cache memory management system when one of the physically-addressed pages has been allocated, deallocated, mapped, or unmapped by the operating system kernel.

23. The electronic device of claim 22, wherein the cache controller of each cache memory management system is configured to designate for eviction all cache lines stored in the respective cache memory device that correspond to one of the plurality of the physically-addressed pages when the operating system kernel communicates that the one of the plurality of the physically-addressed page has been unmapped by the operating system kernel.

24. The electronic device of claim 22, wherein the page status table of each cache memory management system is configured to store data indicating that no other cache memory management system of the central processing unit is currently storing a cache line corresponding to one of the plurality of the physically-addressed pages when the operating system kernel communicates that the one of the plurality of the physically-addressed page has been unmapped by the operating system kernel.

25. The electronic device of claim 22, wherein the cache controller of each cache memory management system is configured to designate as invalid all cache lines stored in the respective cache memory device that correspond to one of the plurality of the physically-addressed pages when the operating system kernel communicates that the one of the plurality of the physically-addressed page has been deallocated by the operating system kernel.

26. The electronic device of claim 22, wherein the cache controller of each cache memory management system is configured to designate as clean all cache lines stored in the respective cache memory device that correspond to one of the plurality of the physically-addressed pages when the operating system kernel communicates that the one of the plurality of the physically-addressed page has been allocated by the operating system kernel.

27. A central processing unit comprising:

a plurality of processors, each processor comprising;

a processor core configured to process data stored in cache lines;

a cache memory device configured to store the cache lines, wherein each cache line corresponds to a line of a page of main memory;

a page status table configured to store information indicating whether any portion of a page of main memory corresponding to a cache line stored in the cache memory device is shared by another processor; and

memory snoop circuitry configured to reference page address bits of a cache tag associated with one of the cache lines but not line number bits of the cache tag when another processor attempts to access the one of the cache lines in main memory.

28. The central processing unit of claim 27, wherein the page status table of each processor is configured to store information indicating whether any portion of a plurality of pages is shared, wherein the plurality of pages comprises a predetermined number of most recently accessed pages.

29. The central processing unit of claim 27, wherein the memory snoop circuitry of each processor is configured to reference the page address bits of the cache tag but not the line number bits of the cache tag when the other processor attempts to access the one of the cache lines in main memory, only when information in the page status table indicates that a page of main memory corresponding to the one of the cache lines is shared by the other processor.