NON-VOLATILE MEMORY GENERATING READ RECLAIM SIGNAL AND MEMORY SYSTEM
First Claim
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1. A non-volatile memory device comprising:
- a memory cell array of nonvolatile memory cells arranged in a plurality of memory blocks;
an error detection and correction (ECC) circuit configured to receive read data from the memory cell array and detect a number of error bits in the read data, wherein the ECC circuit is capable of detecting and correcting a maximum number of error bits;
a counter configured to count a number of detected error bits in the read data and generate an error-possible data indication when a number of counted error bits exceeds a minimum error threshold, wherein the minimum error threshold is less than the maximum number of error bits; and
a read reclaim indicator configured to receive the error-possible data indication and generate read reclaim indication for one of the plurality of memory blocks storing the read data.
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Abstract
A non-volatile memory device includes a memory cell array including memory blocks, an ECC circuit receiving read data from the memory cell array and detecting error bits, wherein the ECC circuit is capable of detecting and correcting a maximum number of error bits, a counter counting detected error bits and generating an error-possible data indication when the counted error bits exceed a minimum error threshold, wherein the minimum error threshold is less than the maximum number of error bits, and a read reclaim indicator receiving the error-possible data indication and generating read reclaim indication for the memory block storing the read data.
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Citations
16 Claims
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1. A non-volatile memory device comprising:
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a memory cell array of nonvolatile memory cells arranged in a plurality of memory blocks; an error detection and correction (ECC) circuit configured to receive read data from the memory cell array and detect a number of error bits in the read data, wherein the ECC circuit is capable of detecting and correcting a maximum number of error bits; a counter configured to count a number of detected error bits in the read data and generate an error-possible data indication when a number of counted error bits exceeds a minimum error threshold, wherein the minimum error threshold is less than the maximum number of error bits; and a read reclaim indicator configured to receive the error-possible data indication and generate read reclaim indication for one of the plurality of memory blocks storing the read data. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A system comprising:
a host controlling operation of a nonvolatile memory device, wherein the nonvolatile memory device comprises; a memory cell array of nonvolatile memory cells arranged in a plurality of memory blocks; an error detection and correction (ECC) circuit configured to receive read data from the memory cell array and detect a number of error bits in the read data, wherein the ECC circuit is capable of detecting and correcting a maximum number of error bits; a counter configured to count a number of detected error bits in the read data and generate an error-possible data indication when a number of counted error bits exceeds a minimum error threshold, wherein the minimum error threshold is less than the maximum number of error bits; and a read reclaim indicator configured to receive the error-possible data indication and provide a read reclaim indication to the host for one of the plurality of memory blocks storing the read data. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
Specification