PACKAGE SUBSTRATE WITH A CAVITY, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

• US 20100236817A1
• Filed: 03/22/2009
• Published: 09/23/2010
• Est. Priority Date: 03/22/2009
• Status: Active Grant

• Current Assignee: Unimicron Technology Corporation
• Original Assignee: Unimicron Technology Corporation
• Inventors: Chen, Tsung-Yuan, Chen, Kuo-Ching, Chien, Cheng-Pin
• Granted Patent: US 8,049,114 B2
• Time in Patent Office: Days
• US Class Current: 174/257
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H05K 1/183 : Components mounted in and supported by recessed areas of the printed circuit board
• CPC Class Codes: H05K 1/186 : manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 2201/0361 : Etched tri-metal structure, i.e. metal layers or metal patterns on both sides of a different central metal layer which is later at least partly etched
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 2203/308 : Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
• CPC Class Codes: H05K 3/06 : the conductive material being removed chemically or electrolytically, e.g. by photo-etch process semi-additive methods H05K3/108
• CPC Class Codes: H05K 3/427 : initial plating of through-holes in metal-clad substrates
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4652 : Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence
• CPC Class Codes: H05K 3/4697 : having cavities, e.g. for mounting components H05K3/4691 takes precedence

Abstract

A method of making a package substrate includes providing a cladding sheet comprising a first metal layer, a second metal layer and an intermediate layer between the first and second metal layers; etching away a portion of the first metal layer to expose a portion of the intermediate layer thereby forming a metal island body; laminating a first copper clad on the cladding sheet comprising a first copper foil and a first insulating layer; patterning the first copper foil to form a first circuit trace; patterning the second metal layer to form a second circuit trace; removing the metal island body to form a cavity in the first insulating layer; and removing the intermediate layer from bottom of the cavity.

Claims

1. A method for fabricating a package substrate, comprising:

providing a cladding sheet having a first metal layer, a second metal layer and an intermediate layer between the first metal layer and the second metal layer;

etching away a portion of the first metal layer to expose a portion of the intermediate layer, thereby forming a metal block;

laminating the cladding sheet with a first copper clad laminate (CCL) comprising a first insulating layer and a first copper foil layer;

patterning the first copper foil layer to form a first trace pattern;

patterning the second metal layer to form a second trace pattern;

removing the metal block to form a cavity; and

removing the intermediate layer from the cavity.

2. The method according to claim 1 wherein the first metal layer is thicker than the second metal layer.

3. The method according to claim 1 wherein the first metal layer comprises copper.

4. The method according to claim 1 wherein the second metal layer comprises copper.

5. The method according to claim 1 wherein the intermediate layer comprises nickel, aluminum, glass fiber, epoxy resin or thermosetting resin.

6. The method according to claim 1 wherein the second trace pattern comprises a plurality of flip-chip bond pads at a bottom of the cavity.

7. The method according to claim 1 further comprising the following step:

forming a plurality of plated through holes in the first insulating layer.

8. The method according to claim 1 further comprising the following steps:

laminating a second CCL on the first trace pattern, wherein the second CCL comprises a second insulating layer and a second copper foil layer, and wherein the second CCL comprises an opening corresponding to the metal block;

forming a plurality of second plated through holes in the second insulating layer; and

patterning the second copper foil layer to form a third trace pattern.

20. The package substrate of claim 19 further comprising a plurality of second plated through holes in the second insulating layer for electrically connecting the first trace pattern with the third trace pattern.

9. A method for fabricating a semiconductor package, comprising:

providing a cladding sheet having a first metal layer, a second metal layer and an intermediate layer between the first metal layer and the second metal layer;

etching away a portion of the first metal layer to expose a portion of the intermediate layer, thereby forming a metal block;

laminating the cladding sheet with a first copper clad laminate (CCL) comprising a first insulating layer and a first copper foil layer;

patterning the first copper foil layer to form a first trace pattern;

patterning the second metal layer to form a second trace pattern, wherein the second trace pattern comprises a plurality of flip-chip bond pads connecting the metal block;

removing the metal block to form a cavity;

removing the intermediate layer from the cavity;

mounting a flip-chip inside the cavity, the flip-chip having an active surface facing the flip-chip bond pads and electrically connecting to the flip-chip bond pads through solder balls; and

filling the cavity with a filler to encapsulate the flip-chip.

10. The method according to claim 9 wherein the first metal layer is thicker than the second metal layer.

11. The method according to claim 9 wherein the first metal layer comprises copper.

12. The method according to claim 9 wherein the second metal layer comprises copper.

13. The method according to claim 9 wherein the intermediate layer comprises nickel, aluminum, glass fiber, epoxy resin or thermosetting resin.

14. The method according to claim 9 further comprising the following step:

forming a plurality of plated through holes in the first insulating layer.

15. The method according to claim 9 further comprising the following steps:

laminating a second CCL on the first trace pattern, wherein the second CCL comprises a second insulating layer and a second copper foil layer, and wherein the second CCL comprises an opening corresponding to the metal block;

forming a plurality of second plated through holes in the second insulating layer; and

patterning the second copper foil layer to form a third trace pattern.

16. The method according to claim 15 further comprising the following step:

stacking an IC package on the third trace pattern.

17. A package substrate with a cavity, comprising:

a first insulating layer;

a cavity in the first insulating layer;

a first trace pattern on one side of the first insulating layer;

a second trace pattern on the other side of the first insulating layer opposite being opposite to the first trace pattern, wherein the second trace pattern comprises a plurality of flip-chip bond pads at a bottom of the cavity, and a portion of the second trace pattern is a dual-layer metal structure comprising a copper layer and an intermediate metal layer; and

a plurality of first plated through holes in the first insulating layer for electrically connecting the first trace pattern with the second trace pattern.

18. The package substrate of claim 17 wherein the intermediate metal layer comprises nickel or aluminum.

19. The package substrate of claim 17 further comprising a second insulating layer covering the first trace pattern, and a third trace pattern on the second insulating layer.