WAFER AND MANUFACTURING METHOD OF ELECTRONIC COMPONENT

• US 20100237345A1
• Filed: 03/18/2009
• Published: 09/23/2010
• Est. Priority Date: 03/18/2009
• Status: Active Grant

• Current Assignee: TDK Corporation
• Original Assignee: TDK Corporation
• Inventors: HACHISUKA, Nozomu, NAKAZAWA, Osamu, HIRAKI, Tetsuya
• Granted Patent: US 8,021,712 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G11B 5/00817 on longitudinal tracks only, e.g. for serpentine format recording
• CPC Class Codes: G11B 5/3993 in semi-conductors
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: Y10T 428/24355 Continuous and nonuniform or irregular surface on layer or component [e.g., roofing, etc.]

Abstract

The present invention relates to a wafer formed with an evaluation element and capable of improving productivity and a manufacturing method of an electronic component using the same. In a wafer according to the present invention, a plurality of elements connected to electrode films through lead-out conductive films are arranged and a chip area is defined for cutting out the plurality of elements in a given number. In the wafer, at least one evaluation element is formed in an area outside the chip area. The lead-out conductive films extend to the outside area and are connected to the evaluation elements. With this wafer, since the lead-out conductor is shared between the element and the evaluation element, the electrode film connected therewith can be shared, too. Accordingly, evaluation can be performed by using the evaluation element without the need of providing the wafer with a lead-out conductor and an electrode film exclusively for the evaluation element, so that the chip area to be cut out from the wafer can be made larger than before.

Claims

1. A wafer comprising a plurality of elements arranged and connected to electrode films through lead-out conductive films and having a chip area defined for cutting out said plurality of elements in a given number,

wherein at least one evaluation element is formed in an area outside said chip area, and

said lead-out conductive films extend to said outside area and are connected to said evaluation element.

2. The wafer of claim 1, wherein said plurality of elements are arranged along a boundary between said chip area and said outside area.

3. The wafer of claim 2, wherein said plurality of elements are arranged at regular intervals.

4. The wafer of claim 3, wherein each of said plurality of elements has a pair of opposed first terminals along said boundary,

said lead-out conductive films and said electrode films are formed for each said first terminal, and

said first terminals are connected to said electrode films through said lead-out conductive films.

5. The wafer of claim 4, wherein said evaluation element has a pair of opposed second terminals along said boundary, and

said pair of second terminals are connected through said lead-out conductive films to different ones of said first terminals that are disposed at two different elements of said plurality of elements.

6. The wafer of claim 5, wherein said two different elements are disposed adjacent each other.

7. The wafer of claim 6, wherein said pair of second terminals are connected to each of two said first terminals that are disposed adjacent each other.

8. The wafer of claim 7, wherein a plurality of said evaluation elements are arranged along said boundary.

9. The wafer of claim 8, wherein said evaluation elements are arranged at regular intervals.

10. The wafer of claim 8, wherein said chip area is to be used for manufacturing a magnetic head, and

each of said plurality of elements is a magneto-resistive effect element and formed in such a manner as to be partially exposed on a section when said chip area is cut out along said boundary.

11. The wafer of claim 10, wherein said dimensions of said evaluation elements are different from each other.

12. The wafer of claim 11, wherein said evaluation elements have smaller dimensions than said plurality of elements in a direction perpendicular to said section.

13. The wafer of claim 8, wherein contact areas of said evaluation elements with said lead-out conductive films are different from each other.

14. The wafer of claim 8, wherein areas of said evaluation elements in a layer plane are different from each other.

15. The wafer of claim 8, wherein at least some of said evaluation elements are connected to each other through a conductive film.

16. A manufacturing method of an electronic component using a wafer including a plurality of elements arranged and connected to electrode films through lead-out conductive films and having a chip area defined for cutting out said plurality of elements in a given number,

wherein at least one evaluation element is formed in an area outside said chip area of said wafer,

said lead-out conductive films extend to said outside area and are connected to said evaluation element, and

wherein the method comprises a step of cutting out said chip area from said wafer.

17. The electronic component manufacturing method of claim 16, wherein said plurality of elements are arranged along a boundary between said chip area and said outside area.

18. The electronic component manufacturing method of claim 17, wherein said plurality of elements are arranged at regular intervals.

19. The electronic component manufacturing method of claim 18, wherein each of said plurality of elements has a pair of opposed first terminals along said boundary, and

said first terminals are connected to said electrode films through said lead-out conductive films.

20. The electronic component manufacturing method of claim 19, wherein said evaluation element has a pair of opposed second terminals along said boundary, and

said pair of second terminals are connected through said lead-out conductive films to different ones of said first terminals that are disposed at two different elements of said plurality of elements.

21. The electronic component manufacturing method of claim 20, wherein said two different elements are disposed adjacent each other.

22. The electronic component manufacturing method of claim 21, wherein said pair of second terminals are connected to each of two said first terminals that are disposed adjacent each other.

23. The electronic component manufacturing method of claim 22, wherein a plurality of said evaluation elements are arranged along said boundary.

24. The electronic component manufacturing method of claim 23, wherein said evaluation elements are arranged at regular intervals.

25. The electronic component manufacturing method of claim 23, wherein said chip area is to be used for manufacturing a magnetic head, and

each of said plurality of elements is a magneto-resistive effect element and formed in such a manner as to be partially exposed on a section when said chip area is cut out along said boundary.

26. The electronic component manufacturing method of claim 25, wherein said dimensions of said evaluation elements are different from each other.

27. The electronic component manufacturing method of claim 26, wherein said evaluation elements have smaller dimensions than said plurality of elements in a direction perpendicular to said section.

28. The electronic component manufacturing method of claim 23, wherein contact areas of said evaluation elements with said lead-out conductive films are different from each other.

29. The electronic component manufacturing method of claim 23, wherein areas of said evaluation elements in a layer plane are different from each other.

30. The electronic component manufacturing method of claim 23, wherein at least some of said evaluation elements are connected to each other through a conductive film.