High Threshold Voltage NMOS Transistors For Low Power IC Technology

• US 20100237425A1
• Filed: 03/19/2010
• Published: 09/23/2010
• Est. Priority Date: 03/20/2009
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Victor W.C., Booth, Roger Allen JR., Vidya, Varadarajan, Yuan, Jun, Kanike, Narasimhulu, Shang, Huiling
• Granted Patent: US 8,969,969 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Abstract

Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

Claims

1. An integrated circuit including

a plurality of transistors of benchmark design of a first conductivity type and including an out-diffusion sink for impurities in a semiconductor material of said transistors of benchmark design, and

at least one transistor of said first conductivity type exhibiting reduced leakage and increased threshold voltage compared with said transistors of benchmark design,

wherein a total impurity dose in a transistor of said benchmark design and in said out-diffusion sink adjacent said transistor of benchmark design and an impurity dose in an impurity implant of said at least one transistor are substantially equal.

2. The integrated circuit as recited in claim 1, wherein said out-diffusion sink comprises a layer or film overlying a portion of a said transistor of benchmark design.

3. The integrated circuit as recited in claim 2, wherein said layer or film is a tensile film.

4. The integrated circuit as recited in claim 3 wherein said tensile film is a tensile nitride film.

5. The integrated circuit as recited in claim 1, wherein said transistors of said benchmark design have a nominal channel length of 40 nm.

6. The integrated circuit as recited in claim 5, wherein said at least one transistor exhibiting reduced leakage has a channel length in excess of 40 nm.

7. The integrated circuit as recited in claim 5, wherein said at least one transistor exhibiting reduced leakage has a nominal channel length of 40 nm.

8. The integrated circuit as recited in claim 1, wherein said impurities in said semiconductor material comprise a halo implant.

9. The integrated circuit as recited in claim 1, wherein said plurality of transistors of benchmark design and said at least one transistor exhibiting reduced leakage are NMOS transistors.

10. The integrated circuit as recited in claim 1, wherein said impurities in said semiconductor material of said transistors of benchmark design include boron.

11. The integrated circuit as recited in claim 1, further including

a plurality of transistors of a second conductivity type.

12. A method of making a semiconductor device having transistors of a first conductivity type but exhibiting different electrical characteristics, said method comprising steps of

forming transistors of a first conductivity type having an impurity region containing an impurity which increases a voltage threshold of said transistors of said first conductivity type,

forming a blanket film covering said transistors of said first conductivity type,

removing a portion of said blanket film from at least one selected transistor, and

out-diffusing an impurity from said impurity region of transistors of said first conductivity type to remaining portions of said blanket film whereby a voltage threshold of transistors of said first conductivity type other than said at least one selected transistor is reduced.

13. The method as recited in claim 12, wherein said impurity region comprises a halo implant.

14. The method as recited in claim 12, including the further steps of

forming a plurality of transistors of a second conductivity type, and

removing portions of said blanket film from transistors of said second conductivity type.

15. The method as recited in claim 14, wherein said step of removing portions of said blanket film from transistors of said second conductivity type includes said step of removing a portion of said blanket film from said selected transistor of said first conductivity type.

16. The method as recited in claim 14, wherein said transistors of said first conductivity type are NMOS transistors.

17. The method as recited in claim 12, wherein said transistors of said first conductivity type are NMOS transistors.

18. The method as recited in claim 12, wherein said step of out-diffusing an impurity includes out-diffusion of boron.

19. The method as recited in claim 12, wherein said step of forming transistors of a first conductivity type includes forming transistors of different gate/channel lengths.