SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20100237432A1
• Filed: 06/03/2010
• Published: 09/23/2010
• Est. Priority Date: 02/23/2009
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: TAKEOKA, Shinji, NAKABAYASHI, Takashi
• Application Number:
  US12/793,613
• Publication Number:
  US 20100237432A1
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

A semiconductor device includes a MIS transistor formed in a FET formation region of a semiconductor substrate, a silicon dioxide film formed in a trench provided in the semiconductor substrate to define the FET formation region, a gate insulating film formed over the FET formation region and the silicon dioxide film, and a gate electrode formed on the gate insulating film. The portion of the gate insulating film formed between the portion of the gate electrode located in the trench and the side surface of the semiconductor substrate contains aluminum, while the portion of the gate insulating film formed between the gate electrode and the upper surface of the semiconductor substrate does not contain aluminum.

Claims

1. A semiconductor device, comprising:

a first MIS transistor formed in a first element formation region of a semiconductor substrate;

an isolation region formed in a trench provided in the semiconductor substrate to define the first element formation region;

a first high-dielectric-constant gate insulating film formed over the first element formation region and the isolation region; and

a first gate electrode formed on the first high-dielectric-constant gate insulating film, wherein

a first portion of the first high-dielectric-constant gate insulating film formed between a portion of the first gate electrode located in the trench and a side surface of the first element formation region contains a first metal, and

a second portion of the first high-dielectric-constant gate insulating film formed between the first gate electrode and an upper surface of the first element formation region does not contain the first metal.

2. The semiconductor device of claim 1, wherein a lowermost surface of a region of the first gate electrode formed on the first portion of the first high-dielectric-constant gate insulating film is at a position lower than a position of the upper surface of the first element formation region.

3. The semiconductor device of claim 1, wherein at least a portion of the second portion of the first high-dielectric-constant gate insulating film spaced apart from the trench does not contain the first metal.

4. The semiconductor device of claim 1, wherein the isolation region has:

an isolation insulating film formed in the trench;

a first underlying insulating film formed between the first element formation region and the isolation insulating film and at a sidewall portion of the trench; and

a first protective film formed between the isolation insulating film and the first underlying insulating film, and containing the first metal.

5. The semiconductor device of claim 4, wherein the first gate electrode is formed on the side surface of the first element formation region with the first underlying insulating film, the first protective film, and the first portion of the first high-dielectric-constant gate insulating film interposed therebetween.

6. The semiconductor device of claim 4, wherein the first underlying insulating film is made of a silicon dioxide film or a silicon oxynitride film.

7. The semiconductor device of claim 4, wherein

the first MIS transistor is an N-channel MIS transistor, and

the first protective film is made of an aluminum film or an aluminum oxide film.

8. The semiconductor device of claim 1, wherein

the first MIS transistor is an N-channel MIS transistor, and

the first metal is aluminum.

9. The semiconductor device of claim 1, wherein

the first MIS transistor is an N-channel MIS transistor, and

the second portion of the first high-dielectric-constant gate insulating film contains any one selected from the group consisting of lanthanum, dysprosium, scandium, erbium, and strontium.

10. The semiconductor device of claim 4, wherein

the first MIS transistor is a P-channel MIS transistor, and

the first protective film is made of a film made of any one selected from the group consisting of lanthanum, dysprosium, scandium, erbium, and strontium or an oxide film of any one selected therefrom.

11. The semiconductor device of claim 1, wherein

the first MIS transistor is a P-channel MIS transistor, and

the first metal is lanthanum, dysprosium, scandium, erbium, or strontium.

12. The semiconductor device of claim 1, wherein

the first MIS transistor is a P-channel MIS transistor, and

the second portion of the first high-dielectric-constant gate insulating film contains aluminum.

13. The semiconductor device of claim 1, wherein

the first high-dielectric-constant gate insulating film is made of a hafnium oxide film, a hafnium silicon oxide film, a hafnium silicon oxynitride film, a zirconium dioxide film, or a hafnium-zirconium oxide film.

14. The semiconductor device of claim 1, wherein

the first gate electrode has a film of at least one of titanium nitride, tantalum nitride, tantalum carbide, and tantalum carbonitride.

15. The semiconductor device of claim 1, wherein

the isolation region defines the first element formation region, and a second element formation region of the semiconductor substrate where a second MIS transistor is formed,

the semiconductor device further comprising:

a second high-dielectric-constant gate insulating film formed over the second element formation region and the isolation region; and

a second gate electrode formed on the second high-dielectric-constant gate insulating film, wherein

a first portion of the second high-dielectric-constant gate insulating film formed between a portion of the second gate electrode located in the trench and a side surface of the second element formation region contains a second metal different from the first metal, and a second portion of the second high-dielectric-constant gate insulating film formed between the second gate electrode and an upper surface of the second element formation region does not contain the second metal.

16. The semiconductor device of claim 15, wherein the isolation region has:

an isolation insulating film formed in the trench;

a first underlying insulating film formed between the first element formation region and the isolation insulating film and at a sidewall portion of the trench;

a first protective film formed between the isolation insulating film and the first underlying insulating film, and containing the first metal;

a second underlying insulating film formed between the second element formation region and the isolation insulating film and at a sidewall portion of the trench; and

a second protective film formed between the isolation insulating film and the second underlying insulating film, and containing the second metal.

17. The semiconductor device of claim 16, wherein

the first MIS transistor is an N-channel MIS transistor,

the second MIS transistor is a P-channel MIS transistor,

the first protective film is made of an aluminum film or an aluminum oxide film, and

the second protective film is made of a film made of any one selected from the group consisting of lanthanum, dysprosium, scandium, erbium, and strontium or an oxide film of any one selected therefrom.

18. The semiconductor device of claim 15, wherein

the first MIS transistor is an N-channel MIS transistor,

the second MIS transistor is a P-channel MIS transistor,

the first metal is aluminum, and

the second metal is lanthanum, dysprosium, scandium, erbium, or strontium.

19. A method for fabricating a semiconductor device comprising a first MIS transistor formed in a first element formation region of a semiconductor substrate, the method comprising the steps of:

(a) forming a trench defining the first element formation region in the semiconductor substrate, and then forming an isolation region in the trench;

(b) forming a first high-dielectric-constant gate insulating film over the first element formation region and the isolation region;

(c) forming a first gate electrode on the first high-dielectric-constant gate insulating film; and

(d) introducing a first metal into a first portion of the first high-dielectric-constant gate insulating film formed between a portion of the first gate electrode located in the trench and a side surface of the first element formation region, wherein,

in the step (d), the first metal is not introduced into a second portion of the first-high-dielectric-constant gate insulating film formed between the first gate electrode and an upper surface of the first element formation region.

20. The method of claim 19, wherein the step (a) has the steps of:

(a1) forming the trench in the semiconductor substrate;

(a2) successively forming a first underlying insulating film and a first protective film containing the first metal at a sidewall portion of the trench in the first element formation region; and

,

(a3) after the step (a2), forming an isolation insulating film to fill the inside of the trench therewith, wherein

the step (d) includes the step of introducing the first metal contained in the first protective film into the first high-dielectric-constant gate insulating film.