METHOD AND STRUCTURE FOR GATE HEIGHT SCALING WITH HIGH-K/METAL GATE TECHNOLOGY
First Claim
Patent Images
1. A method of forming a semiconductor structure, comprising:
- forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor;
selectively removing the dummy gate while protecting the at least one polysilicon feature; and
forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.
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Abstract
A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.
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Citations
20 Claims
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1. A method of forming a semiconductor structure, comprising:
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forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor; selectively removing the dummy gate while protecting the at least one polysilicon feature; and forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of forming a semiconductor device, comprising:
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forming a high-k dielectric layer on a substrate; forming a metal layer on the high-k dielectric layer; forming a silicon layer on the metal layer; forming an etch-stop layer on the silicon layer; forming a polysilicon layer on the etch-stop layer; patterning the polysilicon layer into a dummy gate associated with a transistor and at least one polysilicon feature associated with at least one other device; forming a barrier layer over the substrate, the dummy gate, and the at least one polysilicon feature; removing a portion of the barrier layer from over the dummy gate while masking the barrier layer over the at least one polysilicon feature; selectively removing the dummy gate to expose a portion of the etch-stop layer; removing the exposed portion of the etch-stop layer to expose a portion of the silicon layer; and forming a silicide gate contact from the exposed silicon layer. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A semiconductor structure, comprising:
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a transistor comprising a metal gate on a high-k dielectric, the metal gate comprising a portion of a metal layer and a gate contact; and a device comprising a polysilicon feature formed over a second portion of the metal layer and over a second portion of the high-k dielectric; wherein a height of the metal gate is less than half the height of the polysilicon feature. - View Dependent Claims (18, 19, 20)
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Specification