Chip Inductor With Frequency Dependent Inductance
First Claim
1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design for a semiconductor structure, said design structure comprising:
- a first data representing a dielectric material layer located on a semiconductor substrate;
a second data representing a first metal line embedded in said dielectric material layer;
a third data representing a second metal line embedded in said dielectric material layer and inductively coupled with said first metal line through a portion of said dielectric material layer; and
a fourth data representing a capacitor having a first capacitor electrode and a second capacitor electrode, wherein said first capacitor electrode is resistively connected to an end of said second metal line, and wherein said second capacitor electrode is electrically grounded.
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Accused Products
Abstract
A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.
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Citations
30 Claims
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1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design for a semiconductor structure, said design structure comprising:
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a first data representing a dielectric material layer located on a semiconductor substrate; a second data representing a first metal line embedded in said dielectric material layer; a third data representing a second metal line embedded in said dielectric material layer and inductively coupled with said first metal line through a portion of said dielectric material layer; and a fourth data representing a capacitor having a first capacitor electrode and a second capacitor electrode, wherein said first capacitor electrode is resistively connected to an end of said second metal line, and wherein said second capacitor electrode is electrically grounded. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A semiconductor circuit represented in a circuit schematic or a design structure embodied in a machine readable medium for designing, manufacturing, or testing a design for a semiconductor structure, said semiconductor circuit comprising:
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a signal transmission line having a self-inductance; a first device including a first signal input node directly connected to a first end of said signal transmission line and a second signal input node directly connected to electrical ground; a second device including a first signal output node directly connected to a second end of said signal transmission line and a second signal output node directly connected to electrical ground; a inductive circuit element having a mutual inductance with said signal transmission line through inductive coupling; and a capacitor having a first capacitor node and a second capacitor node, wherein said first capacitor node is directly connected to an end of said inductive circuit element, and wherein said second capacitor node is electrically grounded. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A semiconductor structure comprising:
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a first metal line embedded in a dielectric material layer located on a semiconductor substrate and resistively connected to a first device at a first end of said first metal line and resistively connected to a second device at a second end of said first metal line; a second metal line embedded in said dielectric material layer and inductively coupled with said first metal line through a portion of said dielectric material layer; and a capacitor having a first capacitor electrode and a second capacitor electrode, wherein said first capacitor electrode is resistively connected to an end of said second metal line, and wherein said second capacitor electrode is electrically grounded. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification