Chip Inductor With Frequency Dependent Inductance

• US 20100237464A1
• Filed: 12/07/2009
• Published: 09/23/2010
• Est. Priority Date: 03/18/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ding, Hanyi, Woods, Wayne H. JR.
• Granted Patent: US 8,378,448 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 29/432 Heterojunction gate for field effect devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.

Claims

1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design for a semiconductor structure, said design structure comprising:

a first data representing a dielectric material layer located on a semiconductor substrate;

a second data representing a first metal line embedded in said dielectric material layer;

a third data representing a second metal line embedded in said dielectric material layer and inductively coupled with said first metal line through a portion of said dielectric material layer; and

a fourth data representing a capacitor having a first capacitor electrode and a second capacitor electrode, wherein said first capacitor electrode is resistively connected to an end of said second metal line, and wherein said second capacitor electrode is electrically grounded.

2. The design structure of claim 1, further comprising:

a fifth data representing a first device located on said semiconductor substrate, wherein a first end of said first metal line is resistively connected to said first device; and

a sixth data representing a second device located on said semiconductor substrate, wherein a second end of said first metal line is resistively connected to said second device.

3. The design structure of claim 2, wherein said fifth data represents a signal transmitting device and said sixth data represents a signal receiving device and said second data represents a signal transmission line.

4. The design structure of claim 3, wherein said fifth data includes a seventh data representing a first signal input node structure directly connected to said first end of said first metal line and an eighth data representing a second signal input node structure directly connected to said semiconductor substrate, and wherein said sixth data includes a ninth data representing a first signal output node structure directly connected to said second end of said first metal line and a tenth data representing a second signal output node structure directly connected to said semiconductor substrate.

5. The design structure of claim 1, wherein said fourth data represents a capacitor having an impedance, wherein a magnitude of said impedance is equal to a magnitude of a sum of a first impedance due to self-inductance of said first metal line and a second impedance due to mutual inductance between said first metal line and said second metal line within a frequency range between 1 GHz and 1 THz.

6. The design structure of claim 1, wherein said second data and said third data represent metal lines that are located at a same level within said dielectric material layer and spaced from said semiconductor substrate by a same distance.

7. The design structure of claim 6, wherein said first metal line includes a first sidewall and said second metal line includes a second sidewall, wherein said first and second sidewalls are substantially parallel to each other and abut said portion of said dielectric material layer and laterally separated from each other by a substantially constant spacing.

8. The design structure of claim 1, wherein said second data and said third data represent metal lines that are located at different levels within said dielectric material layer, wherein a vertical spacing between said first metal line and said semiconductor substrate is different from a vertical spacing between said second metal line and said semiconductor substrate.

9. The design structure of claim 1, further comprising an additional data representing a grounded metal line embedded in said dielectric material layer and inductively coupled with said first metal line and grounded to said semiconductor substrate at a first end of said grounded metal line in proximity to said first device and grounded to said semiconductor substrate at a second end of said grounded metal line in proximity to said second device.

10. The design structure of claim 1, wherein said fourth data represents a metal-insulator-metal capacitor (MIMCAP) embedded in said dielectric material layer, wherein said second capacitor electrode is electrically grounded to said semiconductor substrate through at least one conductive via structure within said dielectric material layer.

11. The design structure of claim 1, wherein said fourth data represents a planar capacitor located directly on said semiconductor substrate, wherein said second capacitor electrode is embedded in said semiconductor substrate, wherein said first capacitor electrode vertically abuts a top surface of a node dielectric located directly on said semiconductor substrate, and wherein said node dielectric comprises a same material as, and has a same thickness as, a gate dielectric of a field effect transistor located on said semiconductor substrate.

12. The design structure of claim 1, wherein said fourth data represents a deep trench capacitor located in said semiconductor substrate, wherein said second capacitor electrode abuts and surrounds sidewalls of a deep trench and embedded in said semiconductor substrate, and wherein said first capacitor electrode and a node dielectric are located within said deep trench, and wherein said second end of said second metal line is resistively connected to said first electrode through at least one via structure within said dielectric material layer.

13. The design structure of claim 1, further comprising an additional data representing at least one semiconductor device located on said semiconductor substrate.

14. The design structure of claim 1, further comprising at least one additional data, each representing a capacitively-grounded metal line structure comprising:

an additional metal line embedded in said dielectric layer and inductively coupled with said first metal line through a portion of said dielectric material layer; and

an additional capacitor having a first additional capacitor electrode and a second additional capacitor electrode, wherein said first additional capacitor electrode is resistively connected to an end of said additional metal line, and wherein said second additional capacitor electrode is electrically grounded.

15. A semiconductor circuit represented in a circuit schematic or a design structure embodied in a machine readable medium for designing, manufacturing, or testing a design for a semiconductor structure, said semiconductor circuit comprising:

a signal transmission line having a self-inductance;

a first device including a first signal input node directly connected to a first end of said signal transmission line and a second signal input node directly connected to electrical ground;

a second device including a first signal output node directly connected to a second end of said signal transmission line and a second signal output node directly connected to electrical ground;

a inductive circuit element having a mutual inductance with said signal transmission line through inductive coupling; and

a capacitor having a first capacitor node and a second capacitor node, wherein said first capacitor node is directly connected to an end of said inductive circuit element, and wherein said second capacitor node is electrically grounded.

16. The semiconductor circuit of claim 15, wherein said first device is a signal transmitting device and said second device is a signal receiving device.

17. The semiconductor circuit of claim 15, wherein a magnitude of impedance of said capacitor is equal to a magnitude of a sum of a first impedance due to said self-inductance and a second impedance due to said mutual inductance within a frequency range between 1 GHz and 1 THz.

18. The semiconductor circuit of claim 15, further comprising another inductive circuit element inductively coupled with said signal transmission line and directly connected to said second signal input node and said second signal output node.

19. The semiconductor circuit of claim 15, further comprising:

an additional inductive circuit element having a mutual inductance with said signal transmission line through inductive coupling; and

an additional capacitor having a first additional capacitor node and a second additional capacitor node, wherein said first additional capacitor node is directly connected to an end of said additional inductive circuit element, and wherein said second additional capacitor node is electrically grounded.

20. The semiconductor circuit of claim 15, wherein a total inductance of said signal transmission line as a function of frequency includes divergent singularities between 1 GHz and 1 THz.

21. A semiconductor structure comprising:

a first metal line embedded in a dielectric material layer located on a semiconductor substrate and resistively connected to a first device at a first end of said first metal line and resistively connected to a second device at a second end of said first metal line;

a second metal line embedded in said dielectric material layer and inductively coupled with said first metal line through a portion of said dielectric material layer; and

a capacitor having a first capacitor electrode and a second capacitor electrode, wherein said first capacitor electrode is resistively connected to an end of said second metal line, and wherein said second capacitor electrode is electrically grounded.

22. The semiconductor structure of claim 21, wherein said first device is a signal transmitting device and said second device is a signal receiving device and said first metal line is a signal transmission line.

23. The semiconductor structure of claim 21, wherein said first device includes a first signal input node structure directly connected to said first end of said first metal line and a second signal input node structure directly connected to said semiconductor substrate, and wherein said second device includes a first signal output node structure directly connected to said second end of said first metal line and a second signal output node structure directly connected to said semiconductor substrate.

24. The semiconductor structure of claim 21, wherein said first metal line and said second metal line are located at a same level within said dielectric material layer and spaced from said semiconductor substrate by a same distance.

25. The semiconductor structure of claim 24, wherein said first metal line includes a first sidewall and said second metal line includes a second sidewall, wherein said first and second sidewalls are substantially parallel to each other and abut said portion of said dielectric material layer and laterally separated from each other by a substantially constant spacing.

26. The semiconductor structure of claim 21, wherein said first metal line and said second metal line are located at different levels within said dielectric material layer, wherein a vertical spacing between said first metal line and said semiconductor substrate is different from a vertical spacing between said second metal line and said semiconductor substrate.

27. The semiconductor structure of claim 21, further comprising a grounded metal line embedded in said dielectric material layer and inductively coupled with said first metal line and grounded to said semiconductor substrate at a first end of said grounded metal line in proximity to said first device and grounded to said semiconductor substrate at a second end of said grounded metal line in proximity to said second device or to a system bus ground line.

28. The semiconductor structure of claim 21, further comprising at least one additional capacitively-grounded metal line structure, wherein each of said at least one additional capacitively-grounded line structure comprises:

an additional metal line embedded in said dielectric layer and inductively coupled with said first metal line through a portion of said dielectric material layer; and

an additional capacitor having a first additional capacitor electrode and a second additional capacitor electrode, wherein said first additional capacitor electrode is resistively connected to an end of said additional metal line, and wherein said second additional capacitor electrode is electrically grounded.

29. The semiconductor structure of claim 28, wherein a magnitude of impedance of said additional capacitor is equal to a magnitude of a sum of said first impedance due to self-inductance of said first metal line and third impedance due to mutual inductance between said first metal line and said additional metal line within a frequency range between 1 GHz and 1 THz.

30. The semiconductor structure of claim 28, wherein said first metal line and said additional metal line are located at a same level within said dielectric material layer and spaced from said semiconductor substrate by a same distance.