SYSTEM AND METHOD FOR BIASING CMUT ELEMENTS
First Claim
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1. A system for biasing a capacitive ultrasonic transducer (CMUT) device comprising:
- a circuit includinga CMUT that includes a first plate and a second plate that form a membrane structure;
a circuit voltage source at a complementary metal-oxide-semiconductor (CMOS) compatible voltage;
a bias voltage source that applies a bias voltage greater than a CMOS compatible voltage and is applied to the first plate; and
readout electronics with an input connected on the second plate side of the circuit.
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Abstract
A system and method for biasing a capacitive ultrasonic transducer (CMUT) device with a circuit that includes a CMUT that includes a first plate and a second plate that form a membrane structure; a circuit voltage source at a complementary metal-oxide-semiconductor (CMOS) compatible voltage; a bias voltage source that applies a bias voltage greater than a CMOS compatible voltage and is applied to the first plate; and readout electronics with an input connected on the second plate side of the circuit.
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Citations
19 Claims
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1. A system for biasing a capacitive ultrasonic transducer (CMUT) device comprising:
a circuit including a CMUT that includes a first plate and a second plate that form a membrane structure; a circuit voltage source at a complementary metal-oxide-semiconductor (CMOS) compatible voltage; a bias voltage source that applies a bias voltage greater than a CMOS compatible voltage and is applied to the first plate; and readout electronics with an input connected on the second plate side of the circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for biasing a capacitive ultrasonic transducer (CMUT) device with a first plate and a second plate comprising:
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reading measurements from a connection on the second plate side of the CMUT, wherein the measurements are made with complementary metal-oxide-semiconductor (CMOS) components; biasing the first plate of the CMUT with a voltage source that has a voltage magnitude greater than a CMOS compatible voltage; and blocking the biasing voltage source from the CMOS compatible components. - View Dependent Claims (16, 17, 18, 19)
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Specification