POWER SUPPLY CIRCUIT

• US 20100237847A1
• Filed: 08/03/2007
• Published: 09/23/2010
• Est. Priority Date: 08/04/2006
• Status: Active Grant

• Current Assignee: Zetex Semiconductors PLC
• Original Assignee: Zetex Semiconductors PLC
• Inventors: Finney, Adrian
• Granted Patent: US 8,278,890 B2
• Time in Patent Office: Days
• US Class Current: 323/311
• CPC Class Codes: G01R 19/16519 using FET's
• CPC Class Codes: G01R 19/16547 voltage or current in AC supplies switching for protection H02H; circuits for emergency power supply H02J9/00
• CPC Class Codes: G01R 31/40 Testing power supplies testing photovoltaic devices H02S50/10
• CPC Class Codes: G01R 31/54 Testing for continuity
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H04L 12/10 Current supply arrangements

Abstract

A power supply circuit has a first MOSFET having a body region between the source and drain. The body region is connected so as to be at the same potential as the source. Application of a suitable potential to the gate causes the MOSFET to switch to a conductive on state. The power supply circuit also has signal generation circuitry, which generates a signal indicative of a conductive state of the first MOSFET. The signal generation circuitry generates a reference voltage of a predetermined potential difference from the source potential. The power supply circuit further comprises a second MOSFET having a body region connected so as to be at the same potential as the drain of the first MOSFET, and the second gate is connected to receive the reference voltage. When the potential of the drain of the first MOSFET falls a predetermined voltage below the reference voltage the second MOSFET is switched to a conductive on state between the second source and the second drain, the signal being dependent upon the state of the second MOSFET.

Claims

1. A power supply circuit comprising:

a first power supply rail;

a second power supply rail;

a first MOSFET having a gate, a source, a drain, and a body region between the source and drain, the body region being connected so as to be at the same potential as the source, and the source and drain being connected in series with the second power supply rail, the arrangement being such that application of a suitable potential to the gate is able to switch the MOSFET to an on state in which a conductive channel is opened in the body region between the source and drain to carry a power supply current through the first MOSFET; and

signal generation circuitry arranged to generate a signal indicative of a conductive state of the first MOSFET,

the signal generation circuitry comprising reference voltage generation means connected to said source and arranged to generate a reference voltage, said reference voltage being a predetermined potential difference from the source potential, and a second MOSFET having a second gate, a second source, a second drain, and a second body region between the second source and second drain, the second body region being connected so as to be at the same potential as the drain of the first MOSFET, and the second gate being connected to receive said reference voltage, the arrangement being such that when the potential of the drain of the first MOSFET falls a predetermined voltage below the reference voltage the second MOSFET is switched to an on state in which a second conductive channel is opened in the second body region between the second source and the second drain, the signal being dependent upon the state of the second MOSFET.

2. A circuit in accordance with claim 1, wherein the first MOSFET is a vertical power MOSFET comprising a semiconductor structure having an upper surface and a lower surface, the source of the first MOSFET comprising a conductive contact to the upper surface and the drain of the first MOSFET comprising a conductive contact to the lower surface.

3. A circuit in accordance with claim 1, wherein the second MOSFET is a lateral MOSFET comprising a second semiconductor structure having an upper surface and a lower surface, the source and the drain of the second MOSFET each comprising a respective conductive contact to the upper surface of the second semiconductor structure.

4. A circuit in accordance with claim 1, wherein the first and second MOSFETS are integrated on a common substrate.

5. A circuit in accordance with claim 4, wherein the common substrate has an upper surface and a lower surface and comprises:

a semiconductor substrate of a first conductivity type, a lower surface of the semiconductor substrate being the lower surface of the common substrate;

an epitaxial layer of semiconductor material of the first conductivity type formed on the semiconductor substrate;

a first well of semiconductor material of a second conductivity type extending from the upper surface of the common substrate into the epitaxial layer;

a second well of semiconductor material of said second conductivity type extending from the upper surface of the common substrate into the epitaxial layer, said second well being separate from said first well;

wherein the first MOSFET is a vertical power MOSFET, the source of the first MOSFET comprising a conductive contact to the upper surface of the common substrate arranged to contact the first well and at least one source region of semiconductor material of said first conductivity type extending from the upper surface into the first well, the drain of the first MOSFET comprising a conductive contact to the lower surface of the semiconductor substrate, and the body region of the first MOSFET comprising at least a portion of the first well;

and wherein the second MOSFET is a lateral MOSFET, the source of the second MOSFET comprising a conductive contact to the upper surface of the common substrate arranged to contact a second source region of semiconductor material of said first conductivity type extending from the upper surface into the second well, the drain of the second MOSFET comprising a conductive contact to the upper surface of the common substrate arranged to contact a drain region of semiconductor material of said first conductivity type extending from the upper surface into the second well, and wherein the second body region of the second MOSFET comprises at least part of said second well.

6. A circuit in accordance with claim 5, wherein the first well is formed within an off state depletion region of the first MOSFET such that the surrounding semiconductor material of the first conductivity type is substantially at the source potential of the first MOSFET, and the second well is formed outside the off state depletion region of the first MOSFET such that the surrounding semiconductor material of the first conductivity type is substantially at the drain potential of the first MOSFET.

7. A circuit in accordance with claim 6, comprising a plurality of said first wells and a plurality of said second wells.

8. A circuit in accordance with claim 5, further comprising a termination structure arranged to prevent formation of a conductive channel between the first and second wells.

9. A circuit in accordance with claim 8, wherein the termination structure comprises a channel stop region of semiconductor material of said first conductivity type extending from the upper surface of the common substrate into the epitaxial layer and arranged so as to separate the first and second wells.

10. A circuit in accordance with claim 9, further comprising a short arranged to electrically connect the channel stop region to the second well or to at least one of the plurality of second wells.

11. A circuit in accordance with claim 8, wherein the termination structure comprises a field plate arranged over the upper surface of the common substrate so as to overlap an edge portion of the first well or an edge portion of at least one of the plurality of first wells.

12. A circuit in accordance with claim 5, further comprising gate control circuitry arranged to control the potential applied to the gate of the first MOSFET, the gate control circuitry comprising at least one gate control MOSFET integrated on said common substrate, said gate control MOSFET being a lateral MOSFET comprising a gate, a source, a drain, and a body region between the source and drain, the source of the gate control MOSFET comprising a conductive contact to the upper surface of the common substrate arranged to contact a respective source region of semiconductor material of said first conductivity type extending from the upper surface into the first well, the drain of the gate control MOSFET comprising a conductive contact to the upper surface of the common substrate arranged to contact a respective drain region of semiconductor material of said first conductivity type extending from the upper surface into the first well, and wherein the body region of the gate control MOSFET comprises a portion of said first well or a portion of one of said plurality of first wells.

13. A circuit in accordance with claim 1, wherein the signal generation circuitry comprises at least one further lateral MOSFET having a body region connected so as to be at the same potential as the drain of the first MOSFET.

14. A circuit in accordance with claim 5, wherein the signal generation circuitry comprises at least one further lateral MOSFET having a body region connected so as to be at the same potential as the drain of the first MOSFET and wherein the or each further lateral MOSFET is integrated on the common substrate, and the body region of the or each further lateral MOSFET comprises a respective portion of the second well or of one of the plurality of second wells.

15. A circuit in accordance with claim 13, wherein the at least one further lateral MOSFET comprises a third MOSFET having a drain connected to the first supply rail via at least one resistor and a source connected so as to be at the potential of the drain of the first MOSFET, the third MOSFET being further connected such that it is switched off in response to the second MOSFET switching on, and wherein said signal is a voltage at the drain of the third MOSFET.

16. A circuit in accordance with claim 1, and further comprising a power supply arranged to provide a DC voltage of at least 30V between the first and second power supply rails.

17. A circuit in accordance with claim 16 wherein the power supply is incorporated in a server or a computer.

18. A circuit in accordance with claim 1, further comprising means for connecting an Ethernet cable to the first power supply rail, the drain of the first MOSFET, and to a signal output terminal on which the signal is provided, whereby power and said signal may be provided to a device connected to the circuit via an Ethernet cable.

19. A circuit in accordance with claim 1, in combination with a device arranged to be powered from the power supply rails, the device being connected to the first power supply rail and to the drain of the first MOSFET such that power supply current is supplied to the device through the first MOSFET, and the device being connected to receive said signal, the device having an operational state in which it draws power supply current from the rails and a non-operational state in which it draws at least reduced current from the rails, the device being arranged so as to be dependent upon said signal to switch from the non-operational to the operation state.

20. A power supply circuit and device combination in accordance with claim 19, wherein the device is a DC to DC converter.

21. A method of providing a signal to a device arranged to be powered from power supply rails via a MOSFET, said signal being indicative of a conductive state of the MOSFET, the method comprising the steps of:

monitoring a potential difference between the source and drain of the MOSFET; and

generating said signal according to said potential difference.

22. A method in accordance with claim 21, wherein the step of generating said signal comprises:

generating a reference voltage, said reference voltage being a predetermined potential difference from the source potential of the MOSFET;

applying said reference voltage to the gate of a second MOSFET having a second gate, a second source, a second drain, and a second body region between the second source and second drain;

connecting the second body region so as to be at the same potential as the drain of the first MOSFET,

such that when the potential of the drain of the first MOSFET falls a predetermined voltage below the reference voltage the second MOSFET is switched to an on state in which a second conductive channel is opened in the second body region between the second source and the second drain; and

using the state of the second MOSFET to determine said signal.

23. An integrated circuit comprising:

a common substrate having an upper surface and a lower surface and comprising a semiconductor substrate of a first conductivity type, a lower surface of the semiconductor substrate being the lower surface of the common substrate, and an epitaxial layer of semiconductor material of the first conductivity type formed on the semiconductor substrate;

a first well of semiconductor material of a second conductivity type extending from the upper surface of the common substrate into the epitaxial layer;

a second well of semiconductor material of said second conductivity type extending from the upper surface of the common substrate into the epitaxial layer, said second well being separate from said first well;

a first MOSFET having a gate, a source, a drain, and a body region between the source and drain, the body region being connected so as to be at the same potential as the source;

a second MOSFET having a second gate, a second source, a second drain, and a second body region between the second source and second drain, the second body region being connected so as to be at substantially the same potential as the drain of the first MOSFET,

wherein the first MOSFET is a vertical power MOSFET, the source of the first MOSFET comprising a conductive contact to the upper surface of the common substrate arranged to contact the first well and at least one source region of semiconductor material of said first conductivity type extending from the upper surface into the first well, the drain of the first MOSFET comprising a conductive contact to the lower surface of the semiconductor substrate, and the body region of the first MOSFET comprising at least a portion of the first well;

and wherein the second MOSFET is a lateral MOSFET, the source of the second MOSFET comprising a conductive contact to the upper surface of the common substrate arranged to contact a second source region of semiconductor material of said first conductivity type extending from the upper surface into the second well, the drain of the second MOSFET comprising a conductive contact to the upper surface of the common substrate arranged to contact a drain region of semiconductor material of said first conductivity type extending from the upper surface into the second well, and wherein the second body region of the second MOSFET comprises at least part of said second well.

24. An integrated circuit in accordance with claim 23, wherein the first well is formed within an off state depletion region of the first MOSFET such that the surrounding semiconductor material of the first conductivity type is substantially at the source potential of the first MOSFET, and the second well is formed outside the off state depletion region of the first MOSFET such that the surrounding semiconductor material of the first conductivity type is substantially at the drain potential of the first MOSFET.

26. An integrated circuit in accordance with claim 23, further comprising a termination structure arranged to prevent formation of a conductive channel between the first and second wells.

25. An integrated circuit comprising:

a common substrate having an upper surface and a lower surface and comprising a semiconductor substrate of a first conductivity type, a lower surface of the semiconductor substrate being the lower surface of the common substrate, and an epitaxial layer of semiconductor material of the first conductivity type formed on the semiconductor substrate;

a first well of semiconductor material of a second conductivity type extending from the upper surface of the common substrate into the epitaxial layer;

a second well of semiconductor material of said second conductivity type extending from the upper surface of the common substrate into the epitaxial layer, said second well being separate from said first well;

a first MOSFET having a gate, a source, a drain, and a body region between the source and drain, the body region being connected so as to be at the same potential as the source;

a second MOSFET having a second gate, a second source, a second drain, and a second body region between the second source and second drain,

wherein the first MOSFET is a vertical power MOSFET, the source of the first MOSFET comprising a conductive contact to the upper surface of the common substrate arranged to contact the first well and at least one source region of semiconductor material of said first conductivity type extending from the upper surface into the first well, the drain of the first MOSFET comprising a conductive contact to the lower surface of the semiconductor substrate, and the body region of the first MOSFET comprising at least a portion of the first well;

and wherein the second MOSFET is a lateral MOSFET, the source of the second MOSFET comprising a conductive contact to the upper surface of the common substrate arranged to contact a second source region of semiconductor material of said first conductivity type extending from the upper surface into the second well, the drain of the second MOSFET comprising a conductive contact to the upper surface of the common substrate arranged to contact a drain region of semiconductor material of said first conductivity type extending from the upper surface into the second well, and wherein the second body region of the second MOSFET comprises at least part of said second well,

and wherein the first well is formed within an off state depletion region of the first MOSFET, and the second well is formed outside the off state depletion region of the first MOSFET.