High Performance Output Drivers and Anti-Reflection Circuits

• US 20100237904A1
• Filed: 06/07/2010
• Published: 09/23/2010
• Est. Priority Date: 04/05/2005
• Status: Abandoned Application

• Current Assignee: UniRAM Technology, Inc.
• Original Assignee: UniRAM Technology, Inc.
• Inventors: Shau, Jeng-Jye
• Application Number:
  US12/795,005
• Publication Number:
  US 20100237904A1
• Time in Patent Office: Days
• US Class Current: 326/30
• CPC Class Codes: H03K 19/018585 programmable
• CPC Class Codes: H04L 25/0264 Arrangements for coupling to transmission lines duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end

Abstract

Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s).

Claims

1. A high performance partial voltage interface circuit in a microprocessor comprises an integrated circuit output driver that drives one or a pair of partial voltage interface signal line(s), said output driver comprising:

a first voltage supply source;

a second voltage supply source having a lower potential than said first voltage supply source;

one or more n-channel pull up transistors that couple the partial voltage interface signal line(s) to the first voltage supply source, and provide the majority of driving force to pull the electrical line toward the voltage of the first voltage supply source when the one or more n-channel pull up transistors are on; and

one or more p-channel pull down transistors that couple the partial voltage interface signal line(s) to the second voltage supply source, and provide the majority of driving force to drive the electrical line toward the voltage of the second voltage supply source when the one or more p-channel pull down transistors are on.

2. The partial voltage interface signal line(s) of claim 1 is (are) connected to RC termination circuit(s).

3. The RC termination circuit(s) of claim 2 is (are) embedded in an integrated circuit.

4. The partial voltage interface signal line(s) of claim 1 is (are) connected to RC termination circuit(s) embedded in the microprocessor.

5. The threshold voltage of the n-channel pull up transistor(s) of the output driver in claim 1 is lower than 0.2 volts measured at zero body effect voltage.

6. The threshold voltage of the p-channel pull down transistor(s) of the output driver in claim 1 is more positive than −

0.2 volts measured at zero body effect voltage.

7. The high performance partial voltage interface of claim 1 is compatible with HyperTransport interconnect.

8. The high performance partial voltage interface of claim 1 is compatible with QuickPath Interconnect.

9. The integrated circuit output driver of claim 1 wherein the output driver drives two or more termination circuits.

10. The partial voltage interface signal line(s) of claim 1 is (are) connected to two or more integrated circuit chips.

11. A method to implement a high performance partial voltage interface circuit in a microprocessor comprising the steps of:

providing an integrated circuit output driver comprising one or more n-channel pull up transistors and one or more p-channel pull down transistors;

connecting the output of said integrated output driver to one or a pair of partial voltage interface signal line(s);

providing a first voltage supply source having a first potential coupled to said integrated circuit output driver;

providing a second voltage supply source having a second potential that is lower than the potential of the first voltage supply source;

wherein said one or more n-channel pull up transistors provide the majority of driving force to drive said partial voltage interface signal line(s) towards the first potential when said one or more n-channel pull up transistors are on; and

said one or more p-channel pull down transistors provide the majority of the driving force to drive said partial voltage interface signal line(s) towards the second potential when said one or more p-channel pull down transistors are on.

12. The method in claim 11 further comprising the step of connecting RC termination circuit(s) to the partial voltage interface signal line(s).

13. The method in claim 12 further comprising the step of connecting RC termination circuit(s) embedded in an integrated circuit to the partial voltage interface signal line(s).

14. The method in claim 11 further comprising the step of connecting RC termination circuit(s) embedded in the microprocessor to the partial voltage interface signal line(s).

15. The method in claim 11 further comprising the step of using n-channel pull up transistor(s), with threshold voltage measured at zero body effect voltage lower than 0.2 volts, in the output driver.

16. The method in claim 11 further comprising the step of using p-channel pull up transistor(s), with threshold voltage measured at zero body effect voltage more positive than −

0.2 volts, in the output driver.

17. The method in claim 11 further comprising the step of making the high performance partial voltage interface compatible with HyperTransport interconnect.

18. The method in claim 11 further comprising the step of making the high performance partial voltage interface compatible with QuickPath Interconnect.

19. The method in claim 11 further comprising the step of connecting the integrated circuit output driver to two or more termination circuits.

20. The method in claim 11 further comprising the step of connecting the partial voltage interface signal line(s) to two or more integrated circuit chips.