MULTI-CHIP PACKAGES INCLUDING EXTRA MEMORY CHIPS TO DEFINE ADDITIONAL LOGICAL PACKAGES AND RELATED DEVICES

• US 20100238696A1
• Filed: 03/19/2010
• Published: 09/23/2010
• Est. Priority Date: 03/20/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Baek, Hyunggil
• Granted Patent: US 8,218,346 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48147 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48177 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/48237 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/48599 : Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48699 : Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
• CPC Class Codes: H01L 2224/4911 : the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/49433 : outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1029 : the support being a lead frame
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A packaged integrated circuit device includes a primary chip stack and a secondary chip stack. The primary chip stack includes memory chips therein that define a logical package addressable by a memory controller. The secondary chip stack includes fewer memory chips than the primary chip stack. The memory chips of the secondary chip stack are configured to be electrically connected to memory chips of at least one external device package to define an additional logical package addressable by the memory controller. For example, the additional logical package may include a same number of memory chips as the primary chip stack. Related devices are also discussed.

Claims

1. A packaged integrated circuit device, comprising:

a primary chip stack comprising memory chips therein that define a logical package addressable by a memory controller; and

a secondary chip stack comprising fewer memory chips than the primary chip stack, wherein the memory chips of the secondary chip stack are configured to be electrically connected to memory chips of at least one external device package to define an additional logical package addressable by the memory controller.

2. The device of claim 1, wherein the additional logical package consists of a same number of memory chips as the primary chip stack.

3. The device of claim 1, further comprising:

a package substrate including the primary and secondary chip stacks on a first surface thereof; and

a plurality of electrical terminals on a second surface of the package substrate opposite the first surface,

wherein the chips of the primary chip stack are electrically connected to first ones of the plurality of electrical terminals, and wherein the chips of the secondary chip stack are electrically connected to second ones of the plurality of electrical terminals.

4. The device of claim 3, wherein the second ones of the plurality of electrical terminals are configured to be electrically connected to corresponding terminals of the at least one external device package to define the additional logical package.

5. The device of claim 4, wherein the second ones of the plurality of electrical terminals are provided along edge portions of the substrate.

6. The device of claim 3, wherein the plurality of electrical terminals respectively comprise:

a via portion extending through the package substrate from the second surface to the first surface; and

a ball portion on the second surface of the package substrate and electrically connected to the via portion.

7. The device of claim 3, further comprising:

primary bonding wires electrically connecting the chips of the primary chip stack to the first ones of the plurality of electrical terminals; and

secondary bonding wires electrically connecting the chips of the secondary chip stack to the second ones of the plurality of electrical terminals.

8. The device of claim 3, wherein the primary chip stack comprises:

a first conductive via structure extending through the memory chips thereof and electrically connecting the memory chips of the primary chip stack to the first ones of the plurality of electrical terminals; and

a second conductive via structure extending through the memory chips thereof and electrically connecting the memory chips of the secondary chip stack to the second ones of the plurality of electrical terminals.

9. The device of claim 8, wherein at least one of the memory chips of the secondary chip stack further comprises:

a redistribution line electrically connecting a conductive chip pad thereon to the second conducive via structure.

10. The device of claim 3, wherein the memory chips of the primary chip stack and the memory chips of the secondary chip stack are electrically connected to a common power and/or ground terminal.

11. The device of claim 1, further comprising:

a substrate including the primary and secondary chip stacks thereon;

a primary lead terminal;

a secondary lead terminal electrically isolated from the primary lead terminal;

a primary bonding wire electrically connecting the chips of the primary chip stack to the primary lead terminal; and

a secondary bonding wire electrically connecting the chips of the secondary chip stack to the secondary lead terminal.

12. The device of claim 11, wherein at least one of the chips of the primary and/or secondary chip stacks are provided on opposite surfaces of the substrate.

13. The device of claim 1, further comprising:

a molding compound that encapsulates the primary and secondary chip stacks.

14. A data storage device, comprising:

a plurality of multi-chip packages, each of the plurality of multi-chip packages comprising a primary chip stack and a secondary chip stack having fewer memory chips than the primary chip stack,

wherein the primary chip stacks each define a logical package addressable by a memory controller, and wherein the secondary chip stacks collectively define an additional logical package addressable by the memory controller.

15. The data storage device of claim 14, wherein the additional logical package consists of a same number of memory chips as at least one of the primary chip stacks.

16. The data storage device of claim 14, wherein each of the plurality of multi-chip packages comprises:

a package substrate including the primary and secondary chip stacks on a first surface thereof;

a first plurality of electrical terminals on a second surface of the package substrate opposite the first surface; and

a second plurality of electrical terminals on the second surface of the package substrate,

wherein the chips of the primary chip stack are electrically connected to ones of the first plurality of electrical terminals, and wherein the chips of the secondary chip stack are electrically connected to ones of the second plurality of electrical terminals.

17. The data storage device of claim 16, further comprising:

a motherboard including the plurality of multi-chip packages thereon, wherein the motherboard includes conductive traces configured to electrically connect corresponding ones of the second plurality of electrical terminals of each of the plurality of multi-chip packages to collectively define the additional logical package.

18. The data storage device of claim 17, further comprising:

a memory controller configured to individually address the memory chips of the primary chip stack in each of the plurality of multi-chip packages, and configured to individually address the memory chips of the additional logical package collectively defined by the secondary chip stacks.

19. The data storage device of claim 18, wherein the controller is configured to individually address the memory chips of each primary chip stack and individually address the memory chips of the additional logical package using n address bits, wherein each of the primary chip stacks includes 2″

memory chips, and wherein each of the secondary chip stacks includes 2″

-1 memory chips or less.

20. The data storage device of claim 19, further comprising:

at least one additional multi-chip package, the additional multi-chip package comprising a chip stack including the same number of memory chips as each primary chip stack such that the memory chips of the additional multi-chip package are addressable using the n address bits.