METHOD OF MANUFACTURING POWER SEMICONDUCTOR DEVICE

• US 20100240183A1
• Filed: 09/14/2009
• Published: 09/23/2010
• Est. Priority Date: 03/17/2009
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: NARAZAKI, Atsushi
• Granted Patent: US 8,124,533 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A mask layer having a plurality of openings is formed on the first layer. A second layer having a second conductivity type different from the first conductivity type is formed on the first layer by introducing impurities using the mask layer. A third layer having the first conductivity type is formed on the second layer by introducing impurities using the mask layer. A trench extending through the second layer and the third layer to the first layer is formed by carrying out etching using an etching mask including at least the mask layer. A gate insulation film covering a sidewall of the trench is formed. A trench gate filling the trench is formed on the gate insulation film.

Claims

1. A method of manufacturing a power semiconductor device, comprising the steps of:

preparing a semiconductor substrate having one main surface and an other main surface, and including a first layer having a first conductivity type and located at a side of said one main surface;

forming a mask layer having a plurality of openings on said first layer;

forming a second layer having a second conductivity type different from said first conductivity type on said first layer by introducing impurities using said mask layer;

forming a third layer having said first conductivity type on said second layer by introducing impurities using said mask layer;

forming a trench extending through said second layer and said third layer to said first layer by carrying out etching using an etching mask including at least said mask layer;

forming a gate insulation film covering a sidewall of said trench; and

forming a trench gate filling said trench on said gate insulation film.

2. The method of manufacturing a power semiconductor device according to claim 1, further comprising the step of, after said step of forming said second layer, forming a sidewall film on a sidewall of said mask layer in order to narrow said plurality of openings, wherein

said etching mask includes said sidewall film.

3. The method of manufacturing a power semiconductor device according to claim 1, wherein said step of forming said second layer comprises the step of forming a high concentration region which is higher in impurity concentration at a surface side than said second layer by introducing impurities from each of a pair of openings adjacent to each other among said plurality of openings into a region of said first layer covered with said mask layer.

4. The method of manufacturing a power semiconductor device according to claim 1, wherein

said plurality of openings of said mask layer are arranged at a pitch in one direction and each have a width in said one direction, and

said pitch is smaller than a sum of said width and a value of 1.6 times of a diffusion depth of said second layer.

5. The method of manufacturing a power semiconductor device according to claim 1, further comprising the step of forming a semiconductor region having said second conductivity type on said other main surface of said semiconductor substrate.

6. The method of manufacturing a power semiconductor device according to claim 5, further comprising the step of forming a carrier accumulation layer having said first conductivity type on said first layer by introducing impurities using said mask layer, wherein

said step of forming said second layer is performed by forming said second layer on said first layer with said carrier accumulation layer interposed therebetween.

7. The method of manufacturing a power semiconductor device according to claim 6, wherein said step of forming said carrier accumulation layer is performed using an ion implanter.

8. The method of manufacturing a power semiconductor device according to claim 1, wherein said semiconductor substrate includes a semiconductor region having said second conductivity type and located at a side of said other main surface.

9. The method of manufacturing a power semiconductor device according to claim 8, further comprising the step of forming a carrier accumulation layer having said first conductivity type on said first layer by introducing impurities using said mask layer, wherein

said step of forming said second layer is performed by forming said second layer on said first layer with said carrier accumulation layer interposed therebetween.

10. The method of manufacturing a power semiconductor device according to claim 9, wherein said step of forming said carrier accumulation layer is performed using an ion implanter.