Dual-SiGe Epitaxy for MOS Devices

• US 20100240186A1
• Filed: 05/28/2010
• Published: 09/23/2010
• Est. Priority Date: 12/05/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Yin-Pin
• Granted Patent: US 9,466,716 B2
• Time in Patent Office: Days
• US Class Current: 438/285
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor includes a first stressor region and a second stressor region on the first stressor region, wherein the second stressor region extends laterally closer to a channel region underlying the gate stack than the first stressor region.

Claims

1. A method for forming a semiconductor structure, the method comprising:

providing a semiconductor substrate;

forming a gate stack on the semiconductor substrate; and

forming a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the step of forming the stressor comprises;

forming a first stressor region; and

forming a second stressor region on the first stressor region, wherein the second stressor region extends laterally closer to a channel region underlying the gate stack than the first stressor region.

2. The method of claim 1, wherein the step of forming the stressor comprises:

recessing the semiconductor substrate to form a first recess;

recessing the semiconductor substrate to form a second recess, wherein the second recess is closer to the gate stack than the first recess;

epitaxially growing the first stressor region in the first recess; and

epitaxially growing the second stressor region in the second recess.

3. The method of claim 2, wherein the steps of forming the first and the second recesses comprise:

forming a gate spacer on a sidewall of the gate stack;

forming a disposable spacer on a sidewall of the gate spacer;

forming the first recess along a sidewall of the disposable spacer;

removing the disposable spacer; and

forming the second recess along the sidewall of the gate spacer, wherein the second recess is substantially shallower than the first recess.

4. The method of claim 1, wherein the first stressor region has a first atomic percentage of germanium to germanium and silicon, the second stressor region has a second atomic percentage of germanium to germanium and silicon, and the second atomic percentage is higher than the first atomic percentage.

5. The method of claim 1, wherein the steps of forming the first and the second stressors comprise forming the first stressor using a first flow rate of a Ge-containing precursor, and forming the second stressor using a second flow rate of the Ge-containing precursor, wherein the second flow rate is greater than the first flow rate.

6. The method of claim 1, wherein the first atomic percentage is between about 15 percent and about 25 percent, and wherein the second atomic percentage is between about 25 percent and about 40 percent.

7. The method of claim 1, wherein the first stressor region has a first impurity concentration and the second stressor region has a second impurity concentration, and wherein the second impurity concentration is less than the first impurity concentration.

8. A method of forming a semiconductor structure, the method comprising:

providing a semiconductor substrate;

forming a gate stack on the semiconductor substrate;

forming a gate spacer on a sidewall of the gate stack;

forming a disposable spacer on a sidewall of the gate spacer;

forming a first recess along a sidewall of the disposable spacer;

removing the disposable spacer;

forming a second recess along the sidewall of the gate spacer, wherein the second recess is substantially shallower than the first recess;

forming a first SiGe region in the first recess; and

forming a second SiGe region in the second recess.

9. The method of claim 8, wherein the second SiGe region has a higher germanium concentration of germanium to germanium and silicon than the first SiGe region.

10. The method of claim 9, wherein the step of forming the second SiGe region is performed in a formation environment comprising a higher GeH₄ flow rate than a GeH₄ flow rate used in the step of forming the first SiGe region.

11. The method of claim 8 further comprising doping p-type impurities during the steps of forming the first and the second SiGe regions, wherein the first SiGe region has a first impurity concentration higher than a second p-type impurity concentration in the first SiGe region.

12. The method of claim 11 further comprising implanting a p-type impurity into the first and the second SiGe regions after the steps of forming the first and the second SiGe regions.

13. The method of claim 11, wherein the first p-type impurity concentration is between about 5×

10²⁰/cm³ and about 1×

10²¹/cm³, and the second p-type impurity concentration is between about 1×

10¹⁹/cm³ and about 5×

10²⁰/cm³.

14. A method of forming a transistor, the method comprising:

providing a semiconductor substrate;

forming a gate stack on the semiconductor substrate, the gate stack having vertical sidewalls;

forming gate spacers on the vertical sidewalls of the gate stack;

forming disposable spacers on the vertical sidewalls of the gate spacers;

forming a first recess and a second recess along the sidewalls of the disposable spacers;

removing the disposable spacers;

forming a third recess and a fourth recess along the sidewalls of the gate spacers, wherein the third recess is substantially shallower than the first recess and the fourth recess is substantially shallower than the second recess;

forming a first SiGe region in the first recess;

forming a second SiGe region in the second recess;

forming a third SiGe region in the third recess; and

forming a fourth SiGe region in the fourth recess.

15. The method of claim 14, wherein the first and third SiGe regions form a source/drain for the transistor, and the second and fourth SiGe regions form a drain/source for the transistor.

16. The method of claim 14, wherein the third and fourth SiGe regions have a higher concentration of germanium to germanium and silicon than the first and second SiGe regions.

17. The method of claim 14, wherein the steps of forming the third and fourth SiGe regions are performed in a formation environment comprising a higher GeH₄ flow rate than a GeH₄ flow rate used in the step of forming the first and second SiGe regions.

18. The method of claim 14, further comprising doping p-type impurities during the steps of forming the SiGe regions, wherein the first and second SiGe regions have a first p-type impurity concentration higher than a second p-type impurity concentration in the first and second SiGe regions.

19. The method of claim 18, further comprising implanting a p-type impurity into the first, second, third and fourth SiGe regions after the steps of forming the respective SiGe regions.

20. The method of claim 18, wherein the first p-type impurity concentration is between about 5×

10²⁰/cm³ and about 1×

10²¹/cm³, and the second p-type impurity concentration is between about 1×

10¹⁹/cm³ and about 5×

10²⁰/cm³.