METHODS OF FABRICATING THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES USING EXPANSIONS

• US 20100240205A1
• Filed: 03/09/2010
• Published: 09/23/2010
• Est. Priority Date: 03/19/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Kihyun, Son, Byoungkeun, Kim, Hansoo, Kim, Jinho
• Granted Patent: US 8,338,244 B2
• Time in Patent Office: Days
• US Class Current: 438/588
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/23 with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.

Claims

1. A method of fabricating a three-dimensional nonvolatile memory device, the method comprising:

forming openings penetrating interlayer insulating layers and conductive layers stacked alternately on a substrate;

forming expansions having a diameter wider than that of the openings penetrating the interlayer insulating layers by selectively recessing sidewalls of the conductive layers exposed by the openings;

forming first insulating layers on surfaces of the conductive layers exposed by the expansions;

forming floating gates disposed in the expansions interposing the first insulating layers;

forming second insulating layers on surfaces of the floating gates adjacent to the openings; and

forming semiconductor pillars filling the openings.

2. The method of claim 1, wherein the forming of the expansions includes:

isotropically etching the conductive layers so as to selectively etch the conductive layers more than the substrate and the interlayer insulating layers, and

the forming of the floating gates includes;

forming buried conductive layers filling the openings and the expansions; and

anisotropically etching the buried conductive layers to expose an upper surface of the substrate.

3. The method of claim 1, wherein the forming of the first insulating layers and the second insulating layers includes:

performing an oxidation process or deposition process.

4. The method of claim 1, further comprising:

forming sequentially stacked lower interlayer insulating layers and lower conductive layers including lower openings provided with sidewalls to be connected successively to the openings on the substrate, before forming the openings.

5. The method of claim 1, further comprising:

isolating the interlayer insulating layers and the conductive layers from each other between the semiconductor pillars; and

forming silicide layers on surfaces of the isolated conductive layers.

6-10. -10. (canceled)

11. A method of fabricating a three-dimensional nonvolatile memory device comprising:

forming openings penetrating interlayer insulating layers and conductive layers stacked alternately on a substrate;

then

recessing sidewalls of the conductive layers that are exposed by the openings relative to sidewalls of the interlayer insulating layers that are exposed by the openings to define expansions between portions of adjacent insulating layers that are exposed by the recessing of the sidewalls of the conductive layers;

then

forming floating gates in the expansions; and

then

forming semiconductor pillars in the openings to extend on the floating gates and on the sidewalls of the interlayer insulating layers.

12. The method of claim 11 wherein the following is performed between the recessing sidewalls and the forming floating gates:

forming an insulating layer on the sidewalls of the conductive layers.

13. The method of claim 11 wherein the following is performed between the forming floating gates and the forming semiconductor pillars:

forming an insulating layer on the floating gates, adjacent the openings.

14. The method of claim 12 wherein the following is performed between the forming floating gates and the forming semiconductor pillars:

forming an insulating layer on the floating gates, adjacent the openings.

15. The method of claim 11 wherein recessing sidewalls comprises selectively etching the sidewalls of the conductive layers that are exposed by the openings relative to sidewalls of the interlayer insulating layers that are exposed by the openings.

16. The method of claim 11 wherein forming floating gates in the expansions comprises:

forming a conductive layer in the openings and in the expansions; and

removing the conductive layer from the openings while allowing the conductive layer to remain in the expansions.

17. The method of claim 11 wherein forming openings is preceded by:

sequentially stacking lower insulating layers and lower conductive layers upon one another on the substrate; and

forming lower openings penetrating the lower insulating layers and the lower conductive layers; and

wherein forming openings comprises forming openings penetrating interlayer insulating layers and conductive layers stacked alternately on a substrate and aligned to the lower openings.

18. The method of claim 11 further comprising:

forming a silicide layer on sidewalls of the floating gates opposite the semiconductor pillars.

19. The method of claim 18 wherein forming a silicide layer is preceded by forming a conductive layer on the sidewalls of the floating gates opposite the semiconductor pillars.

20. The method of claim 11 wherein the expansions are ring-shaped expansions surrounding the openings.