INTEGRATED CIRCUIT HAVING A MICROCONTROLLER UNIT AND METHODS OF OPERATION THEREFOR

• US 20100241282A1
• Filed: 10/22/2007
• Published: 09/23/2010
• Est. Priority Date: 10/25/2006
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Mitchell, Ross A., Culshaw, Carl
• Granted Patent: US 8,214,674 B2
• Time in Patent Office: Days
• US Class Current: 700/295
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00

Abstract

Integrated circuit having a Microcontroller Unit and Methods of Operation therefore. An integrated circuit comprises a microcontroller unit with synchronous logic operably coupled to non-clocked intelligent logic. The non-clocked intelligent logic is arranged to autonomously monitor multiple events associated with an operation of the synchronous logic and, in response thereto, the non-clocked intelligent logic initiates autonomously an alternate operational mode of the microcontroller unit. A method of operating a microcontroller unit is also described.

Claims

1. An integrated circuit comprising:

a microcontroller unit with synchronous logic operably coupled to non-clocked intelligent logic, wherein the non-clocked intelligent logic is arranged to autonomously monitor multiple events associated with an operation of the synchronous logic and, in response thereto, the non-clocked intelligent logic initiates autonomously an alternate operational mode of the microcontroller unit.

2. The integrated circuit of claim 1 wherein the alternate operational mode comprises at least one of the group consisting of:

a safety mode;

a low power mode;

a power initiation mode;

a power interruption mode.

3. The integrated circuit of claim 1 wherein the multiple events comprise at least one operational parameter of the synchronous logic being monitored as falling outside of an operational range.

4. The integrated circuit of claim 3 wherein the at least one operational parameter of the synchronous logic comprises at least one of the group consisting of:

a supply voltage threshold;

a supply voltage range;

a temperature threshold;

a temperature range;

a bus clock;

at least one address error condition.

5. The integrated circuit of claim 1 wherein the non-clocked intelligent logic is arranged to force a configurable state on the microcontroller unit thereby autonomously initiating an alternate operational mode of the microcontroller unit.

6. The integrated circuit of claim 1 wherein a memory element and the non-clocked intelligent logic autonomously prevents access to the memory element by the synchronous logic.

7. The integrated circuit of claim 1 wherein a clock source arranged to generate a clock signal to be applied to a central processing unit operably coupled to the synchronous logic and non-clocked intelligent logic wherein, in response to the non-clocked intelligent logic autonomously monitor a clocked event, the non-clocked intelligent logic autonomously halts a synchronous clock signal applied to the central processing unit.

8. The integrated circuit of claim 1 further characterised in that the non-clocked intelligent logic comprises selective logic operably coupled to the synchronous logic, wherein in response to the non-clocked intelligent logic monitoring an event, the selective logic selects and enables synchronous logic that is capable of operating at a low operational supply voltage for one or more microcontroller unit applications.

9. The integrated circuit of claim 1 wherein the non-clocked intelligent logic is arranged to autonomously disable parts of the synchronous logic by holding selected logic modules of the synchronous logic in a reset state.

10. The integrated circuit of claim 9 wherein the non-clocked intelligent logic holds one or more additional logic modules of the synchronous logic in a reset state by disabling one or more clock signal(s) applied to the one or more additional logic modules.

11. The integrated circuit of claim 3 wherein the non-clocked intelligent logic is arranged to identify when the synchronous logic is operating within a desired operational range and, in response thereto, place the microcontroller unit in a normal operational mode.

18. The integrated circuit of claim 2 wherein the multiple events comprise at least one operational parameter of the synchronous logic being monitored as falling outside of an operational range.

19. The integrated circuit of claim 3 wherein the non-clocked intelligent logic is arranged to force a configurable state on the microcontroller unit thereby autonomously initiating an alternate operational mode of the microcontroller unit.

20. The integrated circuit of claim 3 wherein a memory element and the non-clocked intelligent logic autonomously prevents access to the memory element by the synchronous logic.

12. A method of operating a microcontroller unit in a single integrated circuit comprising synchronous logic operably coupled to non-clocked intelligent logic, wherein the method comprises:

monitoring autonomously whether multiple events associated with an operation of the synchronous logic are operating outside of an operational range of the synchronous logic and, in response thereto,

initiating autonomously an alternate operational mode for performing operational functions of the microcontroller unit.

13. An integrated circuit comprising a microcontroller unit having synchronous logic operably coupled to a supply voltage source, wherein the microcontroller unit is comprises non-clocked intelligent power management logic operably coupled to the supply voltage source and arranged to monitor both a load of the microcontroller unit and an output current of the voltage source and in response thereto, the non-clocked intelligent power management logic is arranged to autonomously adapt the voltage regulator output current such that the monitored output current is adjusted to match the monitored load of the microcontroller unit.

14. The integrated circuit of claim 13 wherein the microcontroller unit comprises a central processing unit operably coupled to the supply voltage source, such that the non-clocked intelligent power management logic is arranged to autonomously pass control of the supply voltage source to the central processing unit when the supply voltage is within an operational range of the synchronous logic.

15. The integrated circuit of claim 13 wherein the non-clocked intelligent power management logic autonomously identifies at least one synchronous logic module within the microcontroller unit that require a voltage supply level to operate, and in response thereto, for one or more microcontroller application(s), enables those synchronous logic modules when the voltage supply level increases to the required level.

16. The integrated circuit of claim 13 wherein selective logic operably coupled to the synchronous logic and non-clocked intelligent logic, wherein the non-clocked intelligent logic is arranged to detect whether a supply voltage applied to the synchronous logic has decreased below a threshold and, in response thereto, the selective logic is arranged to select and enable synchronous logic that is capable of operating at the supply voltage below the threshold for one or more respective microcontroller unit applications.

17. A method of operating a microcontroller unit in a single integrated circuit comprising:

synchronous logic and non-clocked intelligent power management logic both operably coupled to a supply voltage source and a load of the microcontroller unit;

monitoring both a load of the microcontroller unit and an output current of the voltage source by the non-clocked intelligent power management logic, and in response thereto,

autonomously adapting the voltage regulator output current, by the non-clocked intelligent power management logic, such that the monitored output current is adjusted to match the monitored load of the microcontroller unit.