MEMORY NODE FOR USE WITHIN A DATA STORAGE SYSTEM HAVING A PLURALITY OF INTERCONNECTED MEMORY NODES

• US 20100241783A1
• Filed: 03/23/2009
• Published: 09/23/2010
• Est. Priority Date: 03/23/2009
• Status: Abandoned Application

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Garcia, Fernando, Hearn, David Christopher
• Application Number:
  US12/409,278
• Publication Number:
  US 20100241783A1
• Time in Patent Office: Days
• US Class Current: 711/5
• CPC Class Codes: G06F 13/1684 using multiple buses

Abstract

A memory node for use within a data storage system having a plurality of interconnected memory nodes is provided. The memory node comprises three data input interfaces, three data output interfaces, a memory module for storing data, and a controller coupled to the three data output interfaces, the three data input interfaces, and the memory module. The controller is configured to receive data via one of the three input interfaces, the data having a predetermined destination, read a first portion of the data to determine if the memory node is the predetermined destination, store a second portion of the data on the memory module, if the memory node is the predetermined destination, and transmit the received data via at least one of the three data output interfaces, if the memory node is not the predetermined destination.

Claims

1. A memory node for use within a data storage system having a plurality of interconnected memory nodes, the memory node comprising:

three data input interfaces;

three data output interfaces;

a memory module for storing data;

a controller coupled to the three data input interfaces, the three data output interfaces, and the memory module, the controller configured to;

receive data via one of the three data input interfaces, the data having a predetermined destination;

read a first portion of the data to determine if the memory node is the predetermined destination;

store a second portion of the data on the memory module, if the memory node is the predetermined destination; and

transmit the received data via at least one of the three data output interfaces, if the memory node is not the predetermined destination.

2. The memory node of claim 1, wherein the controller is further configured to:

receive a data request via one of the three data input interfaces, the data request having a predetermined destination;

read a first portion of the data request to determine if the memory node is the predetermined destination;

retrieve the data from the memory module based on a second portion of the data request, if the memory node is the predetermined destination;

transmit the retrieved data via at least one of the three data output interfaces, if the memory node is not the predetermined destination; and

transmit the data request via at least one of the three data output interfaces, if the memory node is not the predetermined destination.

3. The memory node of claim 2, wherein the controller is further configured to:

receive a status request via one of the three data input interfaces;

generate a status response describing the operational status of the memory node; and

transmit the status response via at least one of the three data output interfaces.

4. The memory node of claim 2, wherein:

the plurality of interconnected memory nodes comprises a three-dimensional array having one or more array inputs and one or more array outputs;

each of the three data input interfaces is coupled to an array input or to a different memory node within the three-dimensional array; and

each of the three data output interfaces is coupled to an array output or to a different memory node within the three-dimensional array.

5. The memory node of claim 4, wherein:

at least one data path exists between each array input and each memory node within the three-dimensional array; and

at least one data path exists between each memory node within the three-dimensional array and each array output.

6. The memory node of claim 5, wherein each memory node within the three-dimensional array is associated with a unique address range, the received data comprises a destination address and payload data, and the controller is further configured to:

store the payload data on the memory module, if the unique address range of the memory node corresponds to the destination address; and

transmit the received data via at least one of the three data output interfaces, if the unique address range of the memory node does not correspond to the destination address.

7. The memory node of claim 6, wherein the received data further comprises data path information and the controller is further configured to:

select one of the three data output interfaces based on the data path information, if the unique address range of the memory node does not correspond to the destination address; and

transmit the received data via the selected one of the three data output interfaces, if the unique address range of the memory node does not correspond to the destination address.

8. The memory node of claim 6, wherein the controller includes a current data output configuration and is further configured to:

select one of the three data output interfaces based on the current data output configuration, if the unique address range of the memory node does not correspond to the destination address; and

transmit the received data via the selected one of the three data output interfaces, if the unique address range of the memory node does not correspond to the destination address.

9. The memory node of claim 5, wherein each memory node within the three-dimensional array is associated with a unique address range, the data request comprises a requested address range, and the controller is further configured to:

retrieve the data from the memory module based on the requested address range, if the requested address range is within the unique address range of the memory node;

transmit the retrieved data via at least one of the three data output interfaces, if the requested address range is within the unique address range of the memory node; and

transmit the data request via at least one of the three data output interfaces, if the requested address range is not within the unique address range of the memory node.

10. The memory node of claim 9, wherein the data request further comprises data path information and the controller is further configured to:

select one of the three data output interfaces based on the data path information;

transmit the retrieved data via the selected one of the three data output interfaces, if the requested address range is within the unique address range of the memory node; and

transmit the data request via the selected one of the three data output interfaces, if the requested address range is not within the unique address range of the memory node.

11. The memory node of claim 10, wherein the controller includes a current data output configuration and is further configured to:

select one of the three data output interfaces based on the current data output configuration;

transmit the retrieved data via at least one of the three data output interfaces, if the requested address range is within the unique address range of the memory node; and

transmit the data request via the selected one of the three data output interfaces, if the requested address range is not within the unique address range.

12. A three-dimensional array of interconnected memory nodes wherein each memory node is associated with a unique address range and comprises:

three data input interfaces;

three data output interfaces;

a memory module for storing data; and

a memory controller coupled to the three data input interfaces, the three data output interfaces, and the memory module, the memory controller configured to;

receive a data packet via one of the three data input interfaces, the data packet comprising a destination address and payload data;

store the payload data on the memory module if the destination address corresponds to the memory node address range;

transmit the received data packet via at least one of the three data output interfaces, if the destination address does not correspond to the memory node address range.

13. The three-dimensional array of claim 12, wherein the memory controller for each memory node is further configured to:

receive a data request via one of the three data input interfaces, the data request comprising a requested address range;

retrieve data from the memory module based on the requested address range, if the requested address range corresponds to the memory node address range;

transmit the retrieved data via at least one of the three data output interfaces, if the requested address range corresponds to the memory node address range; and

transmit the data request via at least one of the three data output interfaces, if the requested address range does not correspond to the memory node address range.

14. The three-dimensional array of claim 13, further comprising:

at least one array input configured to provide the data packet and the data request to the interconnected memory nodes; and

at least one data output configured to receive the retrieved data from the interconnected memory nodes.

15. The three-dimensional array of claim 14, wherein:

the three data input interfaces for each memory module are coupled to an array input or to a different memory node; and

the three data output interfaces for each memory module are coupled to an array output or to a different memory node.

16. The three-dimensional array of claim 15, wherein:

at least one data path exists between each array input and each interconnected memory node; and

at least one data path exists between each interconnected memory node and each array output.

17. A memory node for use within a data storage system having at least one system input interface, at least one system output interface, and a three-dimensional array of interconnected memory nodes that are each associated with a unique address range, the memory node comprising:

three data input interfaces, each coupled to at least one system input interface or to a different memory node within the three-dimensional array;

three data output interfaces, each coupled to at least one system output interface or to a different memory node within the three-dimensional array;

a memory module for storing data;

a controller coupled to the three data input interfaces, the three data output interfaces, and the memory module, the controller configured to;

receive a data packet via one of the three data input interfaces, the data packet comprising a destination address and payload data;

store the payload data on the memory module if the destination address corresponds to the unique address range for the memory node; and

transmit the received data packet via at least one of the three data output interfaces, if the destination address does not correspond to the unique address range for the memory node.

18. The memory node of claim 17, wherein the controller is further configured to:

receive a data request via one of the three data input interfaces, the data request comprising a requested address range;

retrieve the data from the memory module based on the requested address range, if the requested address range is within the unique address range for the memory node;

transmit the retrieved data via at least one of the three data output interfaces, if the requested address range corresponds to the unique address range for the memory node; and

transmit the data request via at least one of the three data output interfaces, if the requested address range does not correspond to the unique address range for the memory node.

19. The memory node of claim 18, wherein the data packet further comprises data path information and the controller is further configured to:

select one of the three data output interfaces based on the data path information, if the destination address does not correspond to the unique address range for the memory node; and

transmit the data packet via the selected one of the three data output interfaces, if the destination address does not correspond to the unique address range for the memory node.

20. The memory node of claim 18, wherein the data request further comprises data path information and the controller is further configured to:

select one of the three data output interfaces based on the requested address range the data path information;

transmit the requested data via the selected one of the three data output interfaces, if the requested address range is within the unique address range for the memory node; and

transmit the data request via the selected one of the three data output interfaces, if the requested address ranged is not within the unique address range for the memory node.