SYSTEM AND METHOD FOR PROVIDING A VIRTUAL MEMORY ARCHITECTURE NARROWER AND DEEPER THAN A PHYSICAL MEMORY ARCHITECTURE

• US 20100241800A1
• Filed: 03/22/2010
• Published: 09/23/2010
• Est. Priority Date: 03/08/2006
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Andrew Caldwell, Brad Hutchings, Herman Schmit, Jason Redgrave, Steve Teig
• Inventors: Teig, Steven, Redgrave, Jason, Caldwell, Andrew, Hutchings, Brad, Schmit, Herman
• Granted Patent: US 7,962,705 B2
• Time in Patent Office: Days
• US Class Current: 711/109
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1776 for memories

Abstract

Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

Claims

1. A method of presenting digital memory to a user design implemented by configurable circuits of an integrated circuit (IC), the method comprising:

reading a multi-bit memory word from a digital memory on the IC;

using a particular set of configurable circuits that are configured as a barrel shifter that shifts said multi-bit memory word to generate a shifted multi-bit word; and

from a plurality of outputs of the barrel shifter, receiving a subset of the bits of said shifted multi-bit word as a narrower multi-bit memory word with fewer bits than the shifted multi-bit word.

2. The method of claim 1, further comprising passing said subset to a set of configurable circuits implementing said user design.

3. The method of claim 1, wherein said subset of the bits of said shifted multi-bit word includes a least significant bit of said shifted multi-bit word.

4. The method of claim 1, wherein said subset of the bits of said shifted multi-bit word includes a most significant bit of said shifted multi-bit word.

5. The method of claim 1, wherein said barrel shifter comprises non-neighboring offset connections.

6. The method of claim 5, wherein said barrel shifter further comprises connections between circuits within a same row or column of circuits.

7. The method of claim 1, further comprising receiving memory address bits.

8. The method of claim 7, wherein said memory address bits comprise a set of bits for identifying a memory location of said multi-bit memory word in the digital memory.

9. The method of claim 8, wherein said memory address bits further comprise a set of bits for determining a number of bits to shift said multi-bit memory word to generate said shifted multi-bit word.

10. The method of claim 1, wherein said barrel shifter comprises at least one multiplexer.

11. The method of claim 1, wherein said barrel shifter comprises at least one look up table.

12. A method of presenting a logical memory as narrower and deeper than a physical memory, the method comprising:

receiving a memory address location comprising a set of P integer bits;

decomposing the set of P bits into a set of N integer real memory address bits and a set of M integer logical memory position bits, wherein N+M=P;

retrieving an original memory word from the physical memory using said set of N bits;

shifting said original memory word by an amount determined by said set of M bits by using a barrel shifter to create a shifted multi-bit word; and

reading a multi-bit part of said shifted multi-bit word without reading the rest of said shifted multi-bit word.

13. The method of claim 12, wherein a width of said original memory word is an integer multiple of a width of said multi-bit part of said shifted multi-bit word.

14. The method of claim 13, wherein said logical memory-position bits represent a binary number.

15. The method of claim 14, wherein said shifting is by a number of bits equal to the width of said multi-bit part of said shifted multi-bit word times said binary number.

16. The method of claim 12, wherein said barrel shifter is implemented on a configurable integrated circuit IC.

17. The method of claim 16, wherein said barrel shifter is implemented using non-neighboring offset connectors.

18. The method of claim 17, wherein said barrel shifter is implemented using connectors that connect two circuits within a same row or column of circuits.

21. The method of claim 12, wherein said physical memory is part of an integrated circuit (IC) that comprises a plurality of configurable circuits, wherein using the barrel shifter comprises using a particular set of configurable circuits that are configured as a barrel shifter that shifts said multi-bit memory word to create said shifted multi-bit word.

19. An integrated circuit (IC) comprising:

a) a digital memory;

b) a set of configurable circuits connected by a plurality of topologically parallel direct offset connections that allow the set of configurable circuits to act as a barrel shifter when said circuits are configured as multiplexers of the barrel shifter, wherein said barrel shifter comprises a set of inputs communicatively connected to said digital memory and said barrel shifter comprises a set of outputs;

c) a first set of circuits for providing memory location bits for identifying a location of a data word within said digital memory; and

d) a second set of circuits for providing memory location bits for determining how much to shift said data word with said barrel shifter, wherein a sub-set of said set of outputs of said barrel shifter is for outputting a narrow data word comprising a portion of said data word.

20. The system of claim 19, wherein said barrel shifter comprises non-neighboring offset connectors.