PROCESSOR, SERVER SYSTEM, AND METHOD FOR ADDING A PROCESSOR

• US 20100241809A1
• Filed: 02/02/2010
• Published: 09/23/2010
• Est. Priority Date: 03/23/2009
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: AGEISHI, DAISUKE
• Granted Patent: US 8,601,215 B2
• Time in Patent Office: Days
• US Class Current: 711/130
• CPC Class Codes: G06F 11/2284 by power-on test, e.g. power-on self test [POST]
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering

Abstract

A processor according to an exemplary of the invention includes a first initialization unit which reads a first program for checking a reliability of the processor into a cache memory and executes the first program when the processor is started up, and a second initialization unit which reads a second program for checking a reliability of the cache memory into a predetermined memory area and executes the second program when the second initialization unit receives a notification indicating the completion of the establishment of a communication path between the predetermined memory area and the processor from another processor which exists in a partition in which the processor is added.

Claims

1. A processor comprising:

a first initialization unit which reads a first program for checking a reliability of said processor into a cache memory and executes said first program when said processor is started up; and

a second initialization unit which reads a second program for checking a reliability of said cache memory into a predetermined memory area and executes said second program when said second initialization unit receives a notification indicating the completion of the establishment of a communication path between said predetermined memory area and said processor from another processor which exists in a partition in which said processor is added.

2. The processor according to claim 1, wherein

said cache memory is included in said processor and said predetermined memory area is included in said another processor which exists in the partition in which said processor is added.

3. The processor according to claim 1, further comprising:

a failure notification control unit which disables a failure notification function provided in the another processor which exists in said partition in which said processor is added when a failure occurs in said memory area during a process performed by said second initialization unit.

4. The processor according to claim 1, further comprising:

an addition cancellation unit which cancels the addition of said processor when a failure occurs in said memory area during the process performed by said second initialization unit.

5. The processor according to claim 4, wherein

said failure notification control unit enables said failure notification function again when the addition of said processor is canceled.

6. The processor according to claim 1, wherein

said processor employs Common System Interface.

7. A server system comprising a first processor and a second processor which exists in a partition in which said first processor is added, wherein

said second processor includes:

a memory allocating unit which allocates a memory area for the initialization of said first processor when a notification indicating the addition of said first processor to the partition in which said second processor exists is received; and

a routing unit which establishes a communication path between said allocated memory area and said first processor and notifies said first processor of the completion of the establishment of the communication path and

said first processor includes;

a first initialization unit which reads a first program for checking the reliability of said first processor into a cache memory and executes said first program when said first processor is started up; and

a second initialization unit which reads a second program for checking the reliability of said cache memory into said memory area and executes said second program when a notification indicating the completion of the establishment of said communication path is received from said second processor.

8. The server system according to claim 7, wherein

said cache memory is included in said first processor and said memory area is included in said second processor.

9. The server system according to claim 7, wherein

said first processor further includes

a failure notification control unit which disables a failure notification function provided in a processor which exists in said partition in which said first processor is added when a failure occurs in said memory area during the process performed by said second initialization unit.

10. The server system according to claim 7, wherein

said first processor further includes

an addition cancellation unit which cancels the addition of the processor when a failure occurs in said memory area during the process performed by said second initialization unit.

11. The server system according to claim 10, wherein

said failure notification control unit enables said failure notification function again when the addition of the processor is canceled.

12. The server system according to claim 7, wherein

said first processor and said second processor each employ Common System Interface.

13. A method for adding a processor comprising the steps of:

reading a first program for checking a reliability of a first processor into a cache memory and executing the first program;

reading a second program for checking a reliability of said cache memory into a predetermined memory area and executing said second program when a notification indicating the completion of the establishment of a communication path between said predetermined memory area and a first processor is received from a second processor which exists in a partition in which said first processor is added.

14. The method for adding a processor according to claim 13, further comprising:

disabling a failure notification function provided in said second processor which exists in said partition in which said first processor is added when a failure occurs in said predetermined memory area during the process for checking the reliability of said cache memory.

15. The method for adding a processor according to claim 13, further comprising:

canceling the addition of said first processor when a failure occurs in said predetermined memory area during the process for checking the reliability of said cache memory.

16. The method for adding a processor according to claim 15, further comprising:

enabling said failure notification function again when the addition of said first processor is canceled.