SYSTEM AND METHOD FOR GENERATING A PLAINTEXT / CYPHERTEXT DATABASE FOR USE IN DEVICE AUTHENTICATION

• US 20100241853A1
• Filed: 03/06/2007
• Published: 09/23/2010
• Est. Priority Date: 03/27/2006
• Status: Active Grant

• Current Assignee: Intertrust Technologies Corporation (Fidelio Acquisition Co LLC)
• Original Assignee: Kyocera Corporation
• Inventors: TAYLOR, John P.
• Granted Patent: US 7,971,058 B2
• Time in Patent Office: Days
• US Class Current: 713/168
• CPC Class Codes: G06F 21/31 User authentication
• CPC Class Codes: G06F 2221/2103 Challenge-response
• CPC Class Codes: G06F 2221/2129 Authenticate client device independently of the user
• CPC Class Codes: H04M 1/72409 by interfacing with external accessories hands-free H04M1/60

Abstract

Plaintext/cyphertext pairs are generated for use in authenticating a device. The device performs a secure authentication algorithm on a secure authentication image file and a received plaintext challenge, and outputs a cyphertext response. If the cyphertext response matches a pre-stored cyphertext string associated with the plaintext challenge, then the device is authenticated. A master processor manages the generation of the plaintext/cyphertext pairs. Plaintext challenges are generated in the master processor using a binary counter and an n-bit key. Each plaintext challenge is transmitted to a first processor and a second processor. The first processor executes the secure authentication algorithm on each plaintext challenge and outputs a cyphertext response associated with each plaintext challenge. The second processor executes the secure authentication algorithm on each plaintext challenge and outputs a second cyphertext response associated with each plaintext challenge. The master processor receives the first and second cyphertext responses for each plaintext challenge. If the first cyphertext response matches the second cyphertext response, then the master processor stores each plaintext challenge and the associated cyphertext response as a vector pair in a database.

Claims

1. A method for generating plaintext/cyphertext pairs for use in authenticating a device having a secure authentication algorithm, the method comprising:

generating a first plaintext challenge in a master processor;

transmitting the first plaintext challenge to a first processor, the first processor executing the secure authentication algorithm;

receiving from the first processor a first cyphertext response;

transmitting the first plaintext challenge to a second processor, the second processor executing the secure authentication algorithm;

receiving from the second processor a second cyphertext response;

comparing the first cyphertext response to the second cyphertext response; and

storing the first plaintext challenge and the first cyphertext response as a vector pair in a database if the first cyphertext response matches the second cyphertext response.

2. The method of claim 1, wherein the transmitting of the first plaintext challenge to the first processor comprises:

transmitting the first plaintext challenge to a first primary slave device;

forwarding the first plaintext challenge from the first primary slave device to a first secondary slave device, wherein the first processor is the first secondary slave device.

3. The method of claim 2, wherein the transmitting of the first plaintext challenge to the second processor comprises:

transmitting the first plaintext challenge to a second primary slave device;

forwarding the first plaintext challenge from the second primary slave device to a second secondary slave device, wherein the first second processor is the second secondary slave device.

4. The method of claim 1, wherein, if the first cyphertext response does not match the second cyphertext response, then:

a. retransmitting the first plaintext challenge to the first processor, the first processor executing the secure authentication algorithm;

b. retransmitting the first plaintext challenge to the second processor, the second processor executing the secure authentication algorithm

c. comparing the first cyphertext response to the second cyphertext response;

d. storing the first plaintext challenge and the first cyphertext response as a vector pair in a database if the first cyphertext response matches the second cyphertext response; and

e. repeating steps a-d for a pre-determined number of times until the first cyphertext response matches the second cyphertext response.

5. The method of claim 1, wherein generating a first plaintext challenge comprises:

incrementing a binary counter to generate a current binary count; and

executing a hash function with an n-bit key on the current binary count;

wherein the result of the execution of the hash function is the first plaintext challenge.

6. The method of claim 5, wherein the binary counter is 64 bit binary counter and the n-bit key is a 128-bit key.

7. The method of claim 5, wherein the binary counter is incremented to generate a next plaintext challenge.

8. The method of claim 1, wherein a first authentication processor group comprises the first processor and the second processor, and wherein the master processor is coupled to a plurality of authentication processors groups comprising the first authentication processor group.

9. The method of claim 8, wherein the master processor is connected to the plurality of authentication processors through a high speed interface to provide efficiency in parallel processing.

10. A system for generating plaintext/cyphertext pairs for use in authenticating a device having a secure authentication algorithm, the system comprising:

a master processor configured to generate a first plaintext challenge, the master processor outputting the first plaintext challenge on a high speed bus;

a database coupled to the master processor;

a first processor connected to the high speed bus, the first processor configured to execute the secure authentication algorithm on the first plaintext challenge and to output a first cyphertext response on the high speed bus;

a second processor connected to the high speed bus, the second processor configured to execute the secure authentication algorithm on the first plaintext challenge and to output a second cyphertext response on the high speed bus;

wherein the master processor is configured to receive the first cyphertext response and the second cyphertext response, to compare the first cyphertext response to the second cyphertext response, and to store the first plaintext challenge and the first cyphertext response as a vector pair in the database if the first cyphertext response matches the second cyphertext response.

11. The system of claim 10, wherein the first processor comprises:

a first primary slave device connected to the high speed bus configured to receive the first plaintext challenge to output the first plaintext challenge to a first multiplexer; and

a first secondary slave device connected to the first multiplexer and configured to receive the first plaintext challenge from the first multiplexer, wherein the first secondary slave device executes the secure authentication algorithm on the first plaintext challenge.

12. The system of claim 10, wherein the second processor comprises:

a second primary slave device connected to the high speed bus configured to receive the first plaintext challenge to output the first plaintext challenge to a second multiplexer; and

a second secondary slave device connected to the second multiplexer and configured to receive the first plaintext challenge from the second multiplexer, wherein the second secondary slave device executes the secure authentication algorithm on the first plaintext challenge.

13. The system of claim 10, wherein the master processor retransmits the first plaintext challenge to the first and second processors if the first cyphertext response does not match the second cyphertext response.

14. The system of claim 10, wherein the master processor further comprises:

a binary counter configured to generate a current binary count; and

a hash program configured to execute a hash function on an n-bit key and the current binary count, and to output the first plaintext challenge.

15. The system of claim 14, wherein the binary counter is 64 bit binary counter and the n-bit key is a 128-bit key.

16. The system of claim 14, wherein the binary counter is incremented to generate a next plaintext challenge.

17. The system of claim 10, wherein a first authentication processor group comprises the first processor and the second processor, and wherein the master processor is coupled to a plurality of authentication processors groups comprising the first authentication processor group via the high speed bus to provide efficiency in parallel processing.

18. The system of claim 10, further comprising a data processing device connected between the database and the master processor.