Communication device employing binary product coding with selective additional Cyclic Redundancy Check (CRC) therein

• US 20100241926A1
• Filed: 03/17/2010
• Published: 09/23/2010
• Est. Priority Date: 03/17/2009
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Fife, James R., Chen, Chung-Jue, Xiao, Kang, Jiang, Hongtao, Wang, Zhongfeng, Bhoja, Sudeep
• Granted Patent: US 8,572,460 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: H03M 13/2963 Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes
• CPC Class Codes: H03M 13/3784 for soft-output decoding of block codes
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0064 Concatenated codes

Abstract

Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel. Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such signals, various bit decisions (within certain iterations) may be selectively ignored and/or reverted back to previous bit decisions.

Claims

1. An apparatus, comprising:

an input for receiving a signal from a communication channel;

a matrix formatting module for arranging a plurality of bits corresponding to the signal into a plurality of matrix formatted bits in accordance with a predetermined pattern;

a plurality of row decoders for decoding a plurality of rows of the plurality of matrix formatted bits thereby generating estimates of information bits encoded within the plurality of rows; and

a plurality of column decoders for decoding a plurality of columns of the plurality of matrix formatted bits thereby generating estimates of information bits encoded within the plurality of columns; and

wherein;

when a row of the plurality of rows being deemed un-decodable in a current decoding iteration, at least one estimate of information bits encoded within the row from at least one prior decoding iteration being selectively recovered for use in subsequent decoding performed by the plurality of column decoders.

2. The apparatus of claim 1, wherein:

when a column of the plurality of columns being deemed un-decodable in the current decoding iteration, at least one estimate of information bits encoded within the column from the prior decoding iteration being selectively recovered for use in subsequent decoding performed by the plurality of row decoders.

3. The apparatus of claim 1, wherein:

when the row of the plurality of rows being deemed un-decodable in the current decoding iteration, the plurality of row decoders ignoring bits within the row affected by the plurality of column decoders from at least one prior decoding iteration.

4. The apparatus of claim 1, wherein:

a row or a column of the plurality of matrix formatted bits includes a control bit that is a cyclic redundancy check (CRC) bit encoded therein or an extra parity bit encoded therein; and

at least one of the plurality of row decoders and the plurality of column decoders includes control bit functionality for processing the at least one row or at least one column of the plurality of matrix formatted bits thereby generating an estimate of the control bit.

5. The apparatus of claim 1, wherein:

each row and each column of the plurality of matrix formatted bits includes at least one respective control bit that is a cyclic redundancy check (CRC) bit encoded therein or an extra parity bit encoded therein; and

at least one of the plurality of row decoders and the plurality of column decoders includes control bit functionality for processing each row and each column of the plurality of matrix formatted bits thereby generating estimates of the respective CRC bits encoded therein.

6. The apparatus of claim 1, wherein:

the plurality of bits corresponding to the signal, including information bits encoded therein in accordance with forward error correction (FEC) coding, includes an overall redundancy being approximately 7%.

7. The apparatus of claim 1, wherein:

information bits within at least one row or at least one column of the plurality of matrix formatted bits being encoded using a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code or a Reed-Solomon (RS) code.

8. The apparatus of claim 1, wherein:

estimates of information bits encoded within one of the plurality of rows, as generated by the plurality of row decoders, being employed to modify a first information bit encoded within a first of the plurality of columns and a second information bit encoded within a second of the plurality of columns.

9. The apparatus of claim 1, wherein:

at least one additional apparatus, communicatively coupled to the apparatus via a communication channel, that performs encoding, by employing a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code or a Reed-Solomon (RS) code, of a plurality of information bits thereby generating a plurality of coded bits; and

the at least one additional apparatus employing the plurality of coded bits thereby generating the signal and launching the signal into the communication channel.

10. The apparatus of claim 1, wherein:

the apparatus being a communication device; and

the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.

11. An apparatus, comprising:

an input for receiving a signal from a communication channel;

a matrix formatting module, communicatively coupled to the input, for arranging a plurality of bits corresponding to the signal into a plurality of matrix formatted bits in accordance with a predetermined pattern such that each row and each column of the plurality of matrix formatted bits includes at least one respective control bit that is a cyclic redundancy check (CRC) bit encoded therein or an extra parity bit encoded therein;

a plurality of row decoders for decoding a plurality of rows of the plurality of matrix formatted bits thereby generating estimates of information bits encoded within the plurality of rows, wherein the plurality of row decoders includes first control bit functionality for generating estimates of the respective control bits encoded within the plurality of rows; and

a plurality of column decoders for decoding a plurality of columns of the plurality of matrix formatted bits thereby generating estimates of information bits encoded within the plurality of columns, wherein the plurality of column decoders includes second control bit functionality for generating estimates of the respective control bits encoded within the plurality of columns; and

wherein;

when a row of the plurality of rows being deemed un-decodable in a current decoding iteration;

at least one estimate of information bits encoded within the row from at least one prior decoding iteration being selectively recovered for use in subsequent decoding performed by the plurality of column decoders; and

the plurality of row decoders ignoring bits within the row affected by the plurality of column decoders from at least one prior decoding iteration.

12. The apparatus of claim 11, wherein:

the plurality of bits corresponding to the signal, including information bits encoded therein in accordance with forward error correction (FEC) coding, includes an overall redundancy being approximately 7%.

13. The apparatus of claim 11, wherein:

information bits within at least one row or at least one column of the plurality of matrix formatted bits being encoded using a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code or a Reed-Solomon (RS) code.

14. The apparatus of claim 11, wherein:

the apparatus being a communication device; and

the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.

15. A method, comprising:

receiving a signal from a communication channel;

arranging a plurality of bits corresponding to the signal into a plurality of matrix formatted bits in accordance with a predetermined pattern;

operating a plurality of row decoders for decoding a plurality of rows of the plurality of matrix formatted bits thereby generating estimates of information bits encoded within the plurality of rows;

operating a plurality of column decoders for decoding a plurality of columns of the plurality of matrix formatted bits thereby generating estimates of information bits encoded within the plurality of columns; and

when a row of the plurality of rows being deemed un-decodable in a current decoding iteration, selectively recovering at least one estimate of information bits encoded within the row from at least one prior decoding iteration for use in subsequent decoding performed by the plurality of column decoders.

16. The method of claim 15, further comprising:

when a column of the plurality of columns being deemed un-decodable in the current decoding iteration, selectively recovering at least one estimate of information bits encoded within the column from the prior decoding iteration for use in subsequent decoding performed by the plurality of row decoders.

17. The method of claim 15, wherein:

when the row of the plurality of rows being deemed un-decodable in the current decoding iteration, operating the plurality of row decoders thereby ignoring bits within the row affected by the plurality of column decoders from at least one prior decoding iteration.

18. The method of claim 15, wherein:

the plurality of bits corresponding to the signal, including information bits encoded therein in accordance with forward error correction (FEC) coding, includes an overall redundancy being approximately 7%.

19. The method of claim 15, further comprising:

encoding information bits within at least one row or at least one column of the plurality of matrix formatted bits using a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code or a Reed-Solomon (RS) code.

20. The method of claim 15, wherein:

the method being performed within a communication device; and

the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.