Soldering Method and Related Device for Improved Resistance to Brittle Fracture

• US 20100243300A1
• Filed: 09/21/2007
• Published: 09/30/2010
• Est. Priority Date: 09/21/2007
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems LLC (Broadcom, Inc.)
• Inventors: Delucca, John, Baiocchi, Frank, Amin, Ahmed, Vaccaro, Brian T., Osenbach, John
• Granted Patent: US 8,242,378 B2
• Time in Patent Office: Days
• US Class Current: 174/257
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H05K 3/244 Finish plating of conductors, especially of copper conductors, e.g. for pads or lands selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3457, e.g. by plating H05K3/3473
• CPC Class Codes: H05K 3/3463 Solder compositions in relation to features of the printed circuit board or the mounting process

Abstract

A lead-free solder joint is formed between a tin-silver-copper solder alloy (SAC), SACX, or other commonly used Pb-free solder alloys, and a metallization layer of a substrate. Interaction of the SAC with the metallization layer forms an intermetallic compound (IMC) that binds the solder mass to the metallization layer. The IMC region is substantially free of any phosphorous-containing layers or regions.

Claims

1. An electronic device comprising:

a core layer;

a nickel layer disposed over at least a portion of the core layer;

a solder mass disposed over at least a portion of the nickel layer; and

an intermetallic compound region coupling the solder mass to the nickel layer, the intermetallic compound region devoid of an effective nickel-phosphorus layer and having no more than 5000 parts per million of phosphorus by weight.

2. The electronic device of claim 1 wherein the intermetallic compound region is devoid of any phosphorus-containing layers thicker than 0.150 μ

m, and is free of any phosphorus-containing regions in excess of 25% of the surface area of the intermetallic compound region and thicker than 0.150 μ

m.

3. The electronic device of claim 1 wherein the intermetallic compound region is devoid of a nickel-phosphorus layer or region having an effective thickness in excess of about 1500 {acute over (Å

)}.

4. The electronic device of claim 1 wherein the intermetallic compound region is devoid of a nickel-phosphorus layer or region having an effective thickness in excess of 150 {acute over (Å

)}.

5. The electronic device of claim 1 wherein the intermetallic compound region is devoid of a nickel-phosphorus layer or region having an effective thickness in excess of 10 {acute over (Å

)}.

6. The electronic device of claim 1 wherein the nickel layer is directly coupled to the intermetallic compound layer and comprises no more than 50 parts per million by weight of phosphorus.

7. The electronic device of claim 1 further comprising a copper layer disposed between the core layer and the nickel layer.

8. The electronic device of claim 7 further comprising a gold layer disposed over at least a portion of the nickel layer, the gold layer comprising no more than 50 parts per million by weight of phosphorus.

9. The electronic device of claim 8 wherein the gold layer comprises no more than 10 parts per million by weight of phosphorus.

10. The electronic device of claim 8 wherein the gold layer is substantially free of phosphorus.

11. A soldering method comprising:

providing a substrate comprising a core layer and at least a nickel layer disposed over at least a portion of the core layer, the nickel layer having no more than a predetermined amount of phosphorus, the predetermined amount adapted to prevent the formation of an effective nickel-phosphorus layer;

contacting together the substrate and a solder mass; and

heating the solder mass to a temperature that is at least a melting point temperature of the solder mass to form an intermetallic compound region that couples the solder mass to the nickel layer.

12. The method of claim 11 wherein the substrate further comprises a gold layer disposed over at least a portion of the nickel layer, the gold layer having no more than another predetermined amount of phosphorus to prevent the formation of the effective nickel-phosphorus layer.

13. The method of claim 12 wherein providing the substrate comprises employing an electroplating procedure to electroplate the gold layer over the nickel layer, the electroplating procedure utilizing an electroplating bath that is substantially free of phosphorus.

14. The method of claim 11 wherein the solder mass comprises at least 90% tin by weight.

15. The method of claim 14 wherein the temperature is at least 230°

C.

16. The method of claim 14 wherein the intermetallic compound region comprises an alloy of nickel and tin, an alloy of nickel, copper and tin, or an alloy of nickel, copper, gold and tin.

17. The method of claim 11 wherein providing the substrate comprises employing an electroplating procedure to electroplate the nickel layer over the core layer, the electroplating procedure utilizing an electroplating bath that is substantially free of phosphorus.

18. The method of claim 17 wherein the substrate further comprises a copper layer disposed between the core layer and the nickel layer, and the nickel layer is electroplated onto the copper layer.

19. An electronic device comprising:

a core layer;

a nickel layer disposed over at least a portion of the core layer;

a solder mass disposed over at least a portion of the nickel layer; and

an intermetallic compound region coupling the solder mass to the nickel layer, the intermetallic compound region substantially free of any nickel-phosphorus layer or region that is thicker than 0.150 μ

m.

20. The electronic device of claim 19 wherein the intermetallic compound region is further substantially free of any nickel-phosphorus layer or region that is thicker than 0.150 μ

m and in excess of 25% of the surface area of the intermetallic compound region.

21. A soldering method comprising:

providing a first electrical component comprising a nickel layer, the nickel layer having no more than a predetermined amount of phosphorus, the predetermined amount adapted to prevent the formation of an effective nickel-phosphorus layer;

providing a second electrical component having an electrical contact;

contacting a solder mass to the first electrical component and the electrical contact; and

heating the solder mass to a temperature that is at least a melting point temperature of the solder mass to form an intermetallic compound region that couples the solder mass to the nickel layer and that couples the solder mass to the electrical contact.

22. The method of claim 21 wherein the nickel layer is disposed within a through hole of a circuit board.

23. The method of claim 21 wherein the nickel layer is disposed over a pad on the circuit board.

24. The method of claim 21 wherein the first electrical component is a circuit board and the second electrical component is a ball grid array device.

25. The method of claim 21 wherein the first electrical component is a circuit board and the second electrical component is a flip-chip device.

26. The method of claim 21 wherein the first electrical component is a flip-chip device and the second electrical component is a flip-chip device.