SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20100244031A1
• Filed: 03/17/2010
• Published: 09/30/2010
• Est. Priority Date: 03/30/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: GODO, Hiromichi, MIYANAGA, Akiharu, AKIMOTO, Kengo
• Granted Patent: US 8,927,981 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The drain voltage of a transistor is determined depending on the driving voltage of an element connected to the transistor. With downsizing of a transistor, intensity of the electric field concentrated in the drain region is increased, and hot carriers are easily generated. An object is to provide a transistor in which the electric field hardly concentrates in the drain region. Another object is to provide a display device including such a transistor. End portions of first and second wiring layers having high electrical conductivity do not overlap with a gate electrode layer, whereby concentration of an electric field in the vicinity of a first electrode layer and a second electrode layer is reduced; thus, generation of hot carriers is suppressed. In addition, one of the first and second electrode layers having higher resistivity than the first and second wiring layers is used as a drain electrode layer.

Claims

1. A semiconductor device comprising:

a gate electrode layer over a substrate;

a gate insulating film over the gate electrode layer;

a first electrode layer and a second electrode layer over the gate insulating film;

a first wiring layer and a second wiring layer over the first electrode layer and the second electrode layer, the first wiring layer being electrically connected to the first electrode layer, and the second wiring layer being electrically connected to the second electrode layer; and

an oxide semiconductor layer over the first wiring layer and the second wiring layer, the oxide semiconductor layer being in contact with a side face and a top face of each of the first electrode layer and the second electrode layer,

wherein the gate electrode layer overlaps with an end portion of each of the first electrode layer and the second electrode layer and does not overlap with the first wiring layer and the second wiring layer,

wherein electrical conductivity of each of the first electrode layer and the second electrode layer is equal to or higher than electrical conductivity of the oxide semiconductor layer, and

wherein electrical conductivity of each of the first electrode layer and the second electrode layer is equal to or lower than electrical conductivity of each of the first wiring layer and the second wiring layer.

2. The semiconductor device according to claim 1, wherein an end portion of the first wiring layer is aligned with one of end portions of the gate electrode layer, and wherein an end portion of the second wiring layer is aligned with the other end portion of the gate electrode layer.

3. The semiconductor device according to claim 1, wherein a thickness of the oxide semiconductor layer is within the range of from 5 nm to 200 nm inclusive, and wherein a thickness of each of the first electrode layer and the second electrode layer is within the range of from 5 nm to 200 nm inclusive.

4. The semiconductor device according to claim 1, wherein the first electrode layer is extended so as to have the end portion positioned more inwardly than an end portion of the first wiring layer and overlap with the gate electrode layer, and wherein the second electrode layer is extended so as to have the end portion positioned more inwardly than an end portion of the second wiring layer and overlap with the gate electrode layer.

5. The semiconductor device according to claim 1, wherein electrical conductivity of each of the first electrode layer and the second electrode layer is within the range of from 1×

10<sup>−

4</sup> S/cm to 1×

10² S/cm inclusive.

6. The semiconductor device according to claim 1, wherein a length of a region where the first electrode layer overlaps with the gate electrode layer and a length of a region where the second electrode layer overlaps with the gate electrode layer are each within the range of from 0.2 μ

m to 5 μ

m inclusive.

7. A semiconductor device comprising:

a first electrode layer and a second electrode layer over a substrate;

a first wiring layer and a second wiring layer over the first electrode layer and the second electrode layer, the first wiring layer being electrically connected to the first electrode layer, and the second wiring layer being electrically connected to the second electrode layer;

an oxide semiconductor layer over the first wiring layer and the second wiring layer, the oxide semiconductor layer being in contact with a side face and a top face of each of the first electrode layer and the second electrode layer;

a gate insulating film over the oxide semiconductor layer; and

a gate electrode layer over the gate insulating film,

wherein the gate electrode layer overlaps with an end portion of each of the first electrode layer and the second electrode layer and does not overlap with the first wiring layer and the second wiring layer,

wherein electrical conductivity of each of the first electrode layer and the second electrode layer is equal to or higher than electrical conductivity of the oxide semiconductor layer, and

wherein electrical conductivity of each of the first electrode layer and the second electrode layer is equal to or lower than electrical conductivity of each of the first wiring layer and the second wiring layer.

8. The semiconductor device according to claim 7, wherein an end portion of the first wiring layer is aligned with one of end portions of the gate electrode layer, and wherein an end portion of the second wiring layer is aligned with the other end portion of the gate electrode layer.

9. The semiconductor device according to claim 7, wherein a thickness of the oxide semiconductor layer is within the range of from 5 nm to 200 nm inclusive, and wherein a thickness of each of the first electrode layer and the second electrode layer is within the range of from 5 nm to 200 nm inclusive.

10. The semiconductor device according to claim 7, wherein the first electrode layer is extended so as to have the end portion positioned more inwardly than an end portion of the first wiring layer and overlap with the gate electrode layer, and wherein the second electrode layer is extended so as to have the end portion positioned more inwardly than an end portion of the second wiring layer and overlap with the gate electrode layer.

11. The semiconductor device according to claim 7, wherein electrical conductivity of each of the first electrode layer and the second electrode layer is within the range of from 1×

10<sup>−

4</sup> S/cm to 1×

10² S/cm inclusive.

12. The semiconductor device according to claim 7, wherein a length of a region where the first electrode layer overlaps with the gate electrode layer and a length of a region where the second electrode layer overlaps with the gate electrode layer are each within the range of from 0.2 μ

m to 5 μ

m inclusive.

13. A method for manufacturing a semiconductor device comprising the steps;

forming a gate electrode layer over a substrate;

forming a gate insulating film over the gate electrode layer;

forming a first electrode layer and a second electrode layer over the gate insulating film;

forming a first wiring layer and a second wiring layer over the first electrode layer and the second electrode layer, the first wiring layer being electrically connected to the first electrode layer, and the second wiring layer being electrically connected to the second electrode layer; and

forming an oxide semiconductor layer over the first wiring layer and the second wiring layer, the oxide semiconductor layer being in contact with a side face and a top face of each of the first electrode layer and the second electrode layer,

wherein the gate electrode layer overlaps with an end portion of each of the first electrode layer and the second electrode layer and does not overlap with the first wiring layer and the second wiring layer,

wherein electrical conductivity of each of the first electrode layer and the second electrode layer is equal to or higher than electrical conductivity of the oxide semiconductor layer, and

wherein electrical conductivity of each of the first electrode layer and the second electrode layer is equal to or lower than electrical conductivity of each of the first wiring layer and the second wiring layer.

14. The method for manufacturing a semiconductor device according to claim 13, wherein an end portion of the first wiring layer is aligned with one of end portions of the gate electrode layer, and wherein an end portion of the second wiring layer is aligned with the other end portion of the gate electrode layer.

15. The method for manufacturing a semiconductor device according to claim 13, wherein a thickness of the oxide semiconductor layer is within the range of from 5 nm to 200 nm inclusive, and wherein a thickness of each of the first electrode layer and the second electrode layer is within the range of from 5 nm to 200 nm inclusive.

16. The method for manufacturing a semiconductor device according to claim 13, wherein the first electrode layer is extended so as to have the end portion positioned more inwardly than an end portion of the first wiring layer and overlap with the gate electrode layer, and wherein the second electrode layer is extended so as to have the end portion positioned more inwardly than an end portion of the second wiring layer and overlap with the gate electrode layer.

17. A method for manufacturing a semiconductor device comprising the steps of:

forming a first electrode layer and a second electrode layer over a substrate;

forming a first wiring layer and a second wiring layer over the first electrode layer and the second electrode layer, the first wiring layer being electrically connected to the first electrode layer, and the second wiring layer being electrically connected to the second electrode layer;

forming an oxide semiconductor layer over the first wiring layer and the second wiring layer, the oxide semiconductor layer being in contact with a side face and a top face of each of the first electrode layer and the second electrode layer;

forming a gate insulating film over the oxide semiconductor layer; and

forming a gate electrode layer over the gate insulating film,

wherein the gate electrode layer overlaps with an end portion of each of the first electrode layer and the second electrode layer and does not overlap with the first wiring layer and the second wiring layer,

wherein electrical conductivity of each of the first electrode layer and the second electrode layer is equal to or higher than electrical conductivity of the oxide semiconductor layer, and

wherein electrical conductivity of each of the first electrode layer and the second electrode layer is equal to or lower than electrical conductivity of each of the first wiring layer and the second wiring layer.

18. The method for manufacturing a semiconductor device according to claim 17, wherein an end portion of the first wiring layer is aligned with one of end portions of the gate electrode layer, and wherein an end portion of the second wiring layer is aligned with the other end portion of the gate electrode layer.

19. The method for manufacturing a semiconductor device according to claim 17, wherein a thickness of the oxide semiconductor layer is within the range of from 5 nm to 200 nm inclusive, and wherein a thickness of each of the first electrode layer and the second electrode layer is within the range of from 5 nm to 200 nm inclusive.

20. The method for manufacturing a semiconductor device according to claim 17, wherein the first electrode layer is extended so as to have the end portion positioned more inwardly than an end portion of the first wiring layer and overlap with the gate electrode layer, and wherein the second electrode layer is extended so as to have the end portion positioned more inwardly than an end portion of the second wiring layer and overlap with the gate electrode layer.