Fabrication and structure of asymmetric field-effect transistors using L-shaped spacers

• US 20100244106A1
• Filed: 03/27/2009
• Published: 09/30/2010
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Bulucea, Constantin, Yang, Jeng-Jiun, French, William D., Johnson, Peter B., Parker, D. Courtney, Bahl, Sandeep R., Archer, Donald M.
• Granted Patent: US 8,101,479 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

Fabrication of an asymmetric field-effect transistor (100) entails defining a gate electrode (262) above, and vertically separated by a gate dielectric layer (260) from, a channel-zone portion (244) of body material of a semiconductor body. Semiconductor dopant is introduced into the body material to define a more heavily doped pocket portion (250) using the gate electrode as a dopant-blocking shield. A spacer (264T) is provided along the gate electrode. The spacer includes (i) a dielectric portion situated along the gate electrode, (ii) a dielectric portion situated along the semiconductor body, and (iii) a filler portion (SC) largely occupying the space between the other two spacer portions. Semiconductor dopant is introduced into the semiconductor body to define a pair of main source/drain portions (240M and 240E) using the gate electrode and the spacer as a dopant-blocking shield. The filler spacer portion is removed to convert the spacer to an L shape (264). A pair of electrical contacts are formed respectively to the main S/D portions.

Claims

1. A method of fabricating a field-effect transistor from a semiconductor body having body material of a first conductivity type, the method comprising:

defining a gate electrode above, and vertically separated by a gate dielectric layer from, a portion of the body material intended to be a channel zone such that the gate electrode has opposing first and second lateral sides;

introducing pocket semiconductor dopant of the first conductivity type into the body material to define a precursor pocket portion of the body material more heavily doped than laterally adjacent material of the body material and substantially extending below only the first of the gate electrode'"'"'s lateral sides using the gate electrode and any material along its lateral sides as a dopant-blocking shield;

providing a first spacer along the gate electrode'"'"'s first lateral side such that the first spacer comprises (i) a first vertically extending dielectric spacer portion situated along the gate electrode, (ii) a first laterally extending dielectric spacer portion continuous with the first vertically extending spacer portion and situated along the semiconductor body, and (iii) a first filler spacer portion largely occupying the space between the first vertically and laterally extending spacer portions;

subsequently introducing main source/drain (“

S/D”

) semiconductor dopant of a second conductivity type opposite to the first conductivity type into the semiconductor body to define first and second main S/D portions of the second conductivity type using the gate electrode, the first spacer, and any other material along the gate electrode'"'"'s lateral sides as a dopant-blocking shield such that (i) the channel zone is situated between the main S/D portions and (ii) a further pocket portion of the first conductivity type comprises material of at least part of the precursor pocket portion and extends to the first main S/D portion for causing the channel zone to be longitudinally asymmetric;

subsequently largely removing the first filler spacer portion; and

forming a pair of electrical contacts respectively to the main S/D portions.

2. A method as in claim 1 further including, between the gate-electrode-defining and spacer-providing acts, introducing first S/D-extension semiconductor dopant of the second conductivity type into the semiconductor body to define a precursor first lateral S/D extension of the second conductivity type using the gate electrode and any material along its lateral sides as a dopant-blocking shield such that, subsequent to the main-S/D-dopant introducing act, (i) a first S/D zone of the second conductivity type comprises the first main S/D portion and a laterally adjoining further first lateral S/D extension more lightly doped than the first main S/D portion and comprised by material of at least part of the precursor first S/D extension and (ii) the further first S/D extension extends laterally partially below the gate electrode.

3. A method as in claim 2 wherein:

the method further includes, between the gate-electrode-defining and spacer-providing acts, introducing second S/D-extension semiconductor dopant of the second conductivity type into the semiconductor body to define a precursor second lateral S/D extension of the second conductivity type using the gate electrode and any material along its lateral sides as a dopant-blocking shield;

the spacer-providing act includes providing a second spacer along the gate electrode'"'"'s second lateral side such that the second spacer comprises (i) a second vertically extending dielectric spacer portion situated along the gate electrode, (ii) a second laterally extending dielectric spacer portion continuous with the second vertically extending spacer portion and situated along the semiconductor body, and (iii) a second filler spacer portion largely occupying the space between the second vertically and laterally extending spacer portions; and

the filler-spacer-portion-removing act includes removing the second filler spacer portion such that, subsequent to the main-S/D-dopant introducing act, (i) a second S/D zone of the second conductivity type comprises the second main S/D portion and a laterally adjoining further second lateral S/D extension more lightly doped than the second main S/D portion and comprised by material of at least part of the precursor second S/D extension, (ii) the further second S/D extension extends laterally partially below the gate electrode, and (iii) the channel zone is terminated by the further S/D extensions along the gate dielectric layer.

4. A method as in claim 2 further including, prior to the spacer-providing act, introducing first well semiconductor dopant of the first conductivity type and second well semiconductor dopant of the second conductivity type into the semiconductor body to respectively define first and second well regions respectively of the first and second conductivity types such the dopants have respective concentrations which reach respective maximum concentrations respectively inside the well regions at a pair of respective laterally extending subsurface locations spaced laterally apart from each other such that, subsequent to the main-S/D-dopant introducing act, (i) the first S/D zone is situated above the subsurface location of the maximum concentration of the first well region, (ii) a second S/D zone of the second conductivity type comprises the second main S/D portion and adjoining material of the second well region outside the second main S/D portion, (iii) the channel zone laterally separates the S/D zones, and (iv) a well-separating portion of the semiconductor body separates the well regions and is more lightly doped than each well region.

5. A method of fabricating a field-effect transistor from a semiconductor body having body material of a first conductivity type, the method comprising:

defining a gate electrode above, and vertically separated by a gate dielectric layer from, a portion of the body material intended to be a channel zone such that the gate electrode has opposite source-side and drain-side lateral sides;

introducing pocket semiconductor dopant of the first conductivity type into the body material to define a precursor source-side pocket portion of the body material more heavily doped than laterally adjacent material of the body material and substantially extending below only the source-side one of the gate electrode'"'"'s lateral sides using the gate electrode and any material along its lateral sides as a dopant-blocking shield;

providing a source-side spacer along the gate electrode'"'"'s source-side lateral side such that the source-side spacer comprises (i) a source-side vertically extending dielectric spacer portion situated along the gate electrode, (ii) a source-side laterally extending dielectric spacer portion continuous with the source-side vertically extending spacer portion and situated along the semiconductor body, and (iii) a source-side filler spacer portion largely occupying the space between the source-side vertically and laterally extending spacer portions;

subsequently introducing main source/drain (“

S/D”

) semiconductor dopant of a second conductivity type opposite to the first conductivity type into the semiconductor body to define main source and drain portions of the second conductivity type using the gate electrode, the source-side spacer, and any other material along the gate electrode'"'"'s lateral sides as a dopant-blocking mask for largely preventing the main S/D dopant from entering the channel zone such that (i) the channel zone is situated between the main source and drain portions and (ii) a further source-side pocket portion of the first conductivity type comprises material of at least part of the precursor pocket portion and extends to the main source portion for causing the channel zone to be longitudinally asymmetric;

subsequently largely removing the source-side filler spacer portion; and

forming a pair of electrical contacts respectively to the main source and drain portions.

6. A method as in claim 5 further including, between the gate-electrode-defining and spacers-providing acts, introducing source-extension semiconductor dopant of the second conductivity type into the semiconductor body to define a precursor lateral source extension of the second conductivity type using the gate electrode and any material along its lateral sides as a dopant-blocking shield for largely preventing the source-extension dopant from passing through the gate dielectric layer such that, subsequent to the main-S/D-dopant introducing act, (i) a source of the first conductivity type comprises the main source portion and a laterally adjoining further lateral source extension more lightly doped than the main source portion and comprised by material of at least part of the precursor source extension and (ii) the further source extension extends laterally partially below the gate electrode.

7. A method as in claim 6 wherein:

the method further includes, between the gate-electrode-defining and spacer-providing acts, introducing drain-extension semiconductor dopant of the second conductivity type into the semiconductor body to define a precursor lateral drain extension of the second conductivity type using the gate electrode and any material along its lateral sides as a dopant-blocking shield for largely preventing the drain-extension dopant from passing through the gate dielectric layer;

the spacer-providing act includes providing a drain-side spacer along the gate electrode'"'"'s drain-side lateral side such that the drain-side spacer comprises (i) a drain-side vertically extending dielectric spacer portion situated along the gate electrode, (ii) a drain-side laterally extending dielectric spacer portion continuous with the drain-side vertically extending spacer portion and situated along the semiconductor body, and (iii) a drain-side filler spacer portion largely occupying the space between the drain-side vertically and laterally extending spacer portions; and

the filler-spacer-portion-removing act includes removing the drain-side filler spacer portion such that, subsequent to the main-S/D-dopant introducing act, (i) a drain of the second conductivity type comprises the main drain portion and a laterally adjoining further lateral drain extension more lightly doped than the main drain portion and comprised by material of at least part of the precursor drain extension, (ii) the further drain extension extends laterally partially below the gate electrode, and (iii) the channel zone is terminated by the further lateral extensions along the gate dielectric layer.

8. A method as in claim 7 wherein:

the source-extension and pocket dopants are both introduced into the semiconductor body through an opening in a first mask; and

the drain-extension dopant is introduced into the semiconductor body through an opening in a second mask.

9. A method as in claim 7 wherein the drain-extension dopant is introduced into the semiconductor body so as to reach a maximum subsurface concentration at a greater average depth into the semiconductor body than the source-extension dopant.

10. A method as in claim 7 wherein the drain-extension-dopant-introducing act comprises implanting ions of a species of the drain-extension dopant at an average tilt angle of at least 15°

relative to a direction generally perpendicular to the gate dielectric layer.

11. A method as in claim 7 wherein the pocket-dopant-introducing act comprises implanting ions of a species of the pocket dopant at an average tilt angle of at least 15°

relative to a direction generally perpendicular to the gate dielectric layer.

12. A method as in claim 7 wherein:

the method further including, prior to the gate-electrode-defining act, introducing primary semiconductor dopant of the first conductivity type into the body material; and

,

subsequent to the contacts-forming act, (i) the semiconductor body has an upper surface, (ii) the body material forms respective pn junctions with the source and drain and extends laterally below both the source and drain, (iii) part of the primary dopant of the first conductivity type is present in the source and drain, (iv) each pn junction reaches a maximum depth below the body'"'"'s upper surface, (v) the primary dopant of the first conductivity type has a concentration which locally reaches a subsurface maximum concentration at a subsurface body-material location extending laterally below largely all of each of the channel, source, and drain and which decreases by at least a factor of 10 in moving upward from the subsurface body-material location along a selected vertical location through the drain to the body'"'"'s upper surface, and (vi) the subsurface body-material location occurs no more than 10 times deeper below the body'"'"'s upper surface than the maximum depth of the pn junction for the drain.

13. A method as in claim 7 wherein:

the main-S/D-dopant-introducing act comprises introducing the main S/D dopant into the semiconductor body at a first dosage and to a first average depth into the semiconductor body; and

the method further includes further includes, between the spacers-providing and filler-spacer-portions-removing acts, introducing lower-portion S/D semiconductor dopant of the second conductivity type into the semiconductor body at a second dosage and to a second average depth into the semiconductor body, the first dosage being greater than the second dosage, the second average depth being greater than the first average depth such that (i) the source includes a lower source portion of the second conductivity type underlying, continuous with, and more lightly doped than the main source portion and (ii) the drain includes a lower drain portion of the second conductivity type underlying, continuous with, and more lightly doped than the main drain portion.

14. A method as in claim 6 further including, prior to the spacers-providing act, introducing first well semiconductor dopant of the first conductivity type and second well semiconductor dopant of the second conductivity type into the semiconductor body to respectively define first and second well regions respectively of the first and second conductivity types such that, subsequent to the main-dopant introducing act, (i) the well dopants have respective concentrations which reach respective subsurface maximum concentrations respectively inside the well regions at a pair of respective laterally extending subsurface locations spaced laterally apart from each other, (ii) the source is situated above the subsurface location of the maximum concentration of the first well region, (iii) the channel zone comprises part of the first well region, (iv) a drain of the second conductivity type comprises the second main drain portion and adjoining material of the second well region outside the second main drain portion, (v) the channel zone laterally separates the source and drain, and (vi) a well-separating portion of the semiconductor body separates the well regions and is more lightly doped than each well region.

15. A method as in claim 14 further including, prior to the gate-electrode-defining act, forming an electrically insulating region recessed into the semiconductor body along its upper surface such that, subsequent to the main-dopant introducing act, the recessed insulating region extends into second well region to laterally surround the main drain portion and laterally separate it from material of the second well region continuous with the well-separating portion and such that the gate electrode extends over the recessed insulating region partway to the main drain portion.

16. A method as in claim 14 wherein the pocket-dopant-introducing act comprises implanting ions of a species of the pocket dopant at an average tilt angle of at least 15°

relative to a direction generally perpendicular to the gate dielectric layer.

17. A method as in claim 14 wherein the well-separating portion is of the first conductivity type and extends to the gate dielectric layer such that the channel zone includes at least part of the well-separating portion.

18. A method as in claim 14 wherein the well-separating portion comprises a lower section of the first conductivity type and an upper section of the second conductivity type situated between the lower section and the gate dielectric layer such that the drain further includes at least part of the upper section of the well-separating portion.

19. A method as in claim 14 wherein all semiconductor dopant of the second conductivity type in the second well region has a concentration that decreases by at least a factor of 10 in moving upward from the subsurface location of the maximum concentration of the second well region along a selected vertical location through the second well region to the gate dielectric layer, the subsurface location of the maximum concentration of the second well region occurring no more than 10 times deeper below the gate dielectric layer than the maximum depth to which the source extends below the gate dielectric layer.

20. A method as in claim 19 wherein all semiconductor dopant of the first conductivity type in the first well region has a concentration that decreases by at least a factor of 10 in moving upward from the subsurface location of the maximum concentration of the first well region along a selected vertical location through the first well region to the gate dielectric layer, the subsurface location of the maximum concentration of the first well region n occurring no more than 10 times deeper below the gate dielectric layer than the maximum depth to which the source extends below the gate dielectric layer.

21. A method as in claim 6 wherein the transistor is a p-channel transistor.

22. A method as in claim 21 wherein:

the pocket-dopant-introducing act comprises ion implanting a species of the pocket dopant into the semiconductor body; and

the pocket dopant comprises arsenic.

23. A method as in claim 6 wherein the contacts-forming act comprises reacting metal with semiconductor material of the source and drain to form a contact layer of a metal-semiconductor compound along remaining material of each of the source and drain.

24. A method as in claim 6 wherein the source-side filler spacer portion consists largely of dielectric material.

25. A method as in claim 6 wherein:

the vertically extending portion of the source-side spacer comprises a first vertically extending layer and a second vertically extending layer chemically different from the first vertically extending layer such that the first vertically extending layer is situated between the gate electrode and the second vertically extending layer; and

the laterally extending portion of the source-side spacer comprises a first laterally extending layer and a second laterally extending layer chemically different from the first laterally extending layer such that the first laterally extending layer is situated between the gate electrode and the second laterally extending layer.

26. A method as in claim 25 wherein:

the first layers of the source-side spacer comprise semiconductor oxide; and

the second layers of the source-side spacer comprise semiconductor nitride.

27. A structure comprising a field-effect transistor provided along an upper surface of a semiconductor body having body material of a first conductivity type, the transistor comprising:

a channel zone of the body material;

a gate dielectric layer overlying the channel zone;

a gate electrode overlying the gate dielectric layer above the channel zone and having opposing first and second lateral sides;

first and second source/drain (“

S/D”

) zones situated in the semiconductor body along its upper surface, laterally separated by the channel zone, extending respectively below the gate electrode'"'"'s first and second lateral sides, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body material, a pocket portion of the body material more heavily doped than laterally adjacent material of the body material extending largely along only the first S/D zone and into the channel zone so as to cause the channel zone to be asymmetric with respect to the S/D zones;

a first spacer situated laterally along the gate electrode'"'"'s first lateral side and comprising (i) a first vertically extending dielectric spacer portion situated along the gate electrode and (ii) a second laterally extending dielectric spacer portion continuous with the first vertically extending spacer portion and situated along the semiconductor body so as to generally form an L with the first vertically extending spacer portion; and

a pair of electrical contacts respectively to the S/D zones.

28. A structure as in claim 27 wherein the first S/D zone comprises a first main S/D portion and a first lateral S/D extension laterally continuous with the first main S/D portion, more lightly doped than the first main S/D portion, and extending laterally under the gate electrode'"'"'s first lateral side.

29. A structure as in claim 28 wherein:

the second S/D zone comprises a second main S/D portion and a second lateral S/D extension laterally continuous with the second main S/D portion, more lightly doped than the second main S/D portion, and extending laterally under the gate electrode'"'"'s second lateral side such that the lateral extensions terminate the channel zone along the body'"'"'s upper surface; and

the structure includes a second spacer situated laterally along the gate electrode'"'"'s second lateral side and comprising (i) a first vertically extending dielectric spacer portion situated along the gate electrode and (ii) a second laterally extending dielectric spacer portion continuous with the first vertically extending spacer portion of the second spacer and situated along the semiconductor body so as to generally form an L with the first vertically extending spacer portion of the second spacer.

30. A structure as in claim 28 wherein the semiconductor body further includes first and second well regions defined respectively by first and second well dopants of the first and second conductivity types so as to be respectively of the first and second conductivity types such that (i) the well dopants have respective concentrations which reach respective maximum concentrations respectively inside the well regions at a pair of respective laterally extending subsurface locations spaced laterally apart from each other, (ii) the first S/D zone is situated above the subsurface location of the maximum concentration of the first well region, (iii) the second S/D zone comprises a second main S/D portion and adjoining material of the second well region outside the second main S/D portion, and (iv) a well-separating portion of the semiconductor body separates the well regions and is more lightly doped than each well region.

31. A structure comprising a field-effect transistor provided along an upper surface of a semiconductor body having body material of a first conductivity type, the transistor comprising:

a channel zone of the body material;

a gate dielectric layer overlying the channel zone;

a gate electrode overlying the gate dielectric layer above the channel zone and having opposing source-side and drain-side lateral sides;

a source and a drain situated in the semiconductor body along its upper surface, laterally separated by the channel zone, extending respectively below the gate electrode'"'"'s source-side and drain-side lateral sides, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body material, a pocket portion of the body material more heavily doped than laterally adjacent material of the body material extending largely along only the source and into the channel zone so as to cause the channel zone to be asymmetric with respect to the source and drain;

a source-side spacer situated laterally along the gate electrode'"'"'s source-side lateral side and comprising (i) a source-side vertically extending dielectric spacer portion situated along the gate electrode and (ii) a source-side laterally extending dielectric spacer portion continuous with the source-side vertically extending spacer portion and situated along the semiconductor body so as to generally form an L with the source-side vertically extending spacer portion; and

a pair of electrical contacts respectively to the source and drain.

32. A structure as in claim 31 wherein the source comprises a main source portion and a lateral source extension laterally continuous with the main source portion, more lightly doped than the main source portion, and extending laterally under the gate electrode'"'"'s source-side lateral side.

33. A structure as in claim 32 wherein:

the drain comprises a main drain portion and a lateral drain extension laterally continuous with the main drain portion, more lightly doped than the main drain portion, and extending laterally under the gate electrode'"'"'s drain-side lateral side such that the lateral extensions terminate the channel zone along the body'"'"'s upper surface; and

the structure includes a drain-side spacer situated laterally along the gate electrode'"'"'s drain-side lateral side and comprising (i) a drain-side vertically extending dielectric spacer portion situated along the gate electrode and (ii) a drain-side laterally extending dielectric spacer portion continuous with the drain-side vertically extending spacer portion and situated along the semiconductor body so as to generally form an L with the drain-side vertically extending spacer portion.

34. A structure as in claim 33 wherein the lateral drain extension extends deeper below the body'"'"'s upper surface than the lateral source extension.

35. A structure as in claim 33 wherein:

semiconductor dopant of the first conductivity type is present in the source and drain;

each pn junction reaches a maximum depth below the body'"'"'s upper surface;

all semiconductor dopant of the first conductivity type in the semiconductor body has a concentration which locally reaches a subsurface maximum concentration at a subsurface body-material location extending laterally below largely all of each of the channel, source, and drain and which decreases by at least a factor of 10 in moving upward from the subsurface body-material location along a selected vertical location through the drain to the body'"'"'s upper surface; and

the subsurface body-material location occurs no more than 10 times deeper below the body'"'"'s upper surface than the maximum depth of the pn junction for the drain.

36. A structure as in claim 33 wherein:

the source includes a lower source portion of the second conductivity type underlying, continuous with, and more lightly doped than the main source portion; and

the drain includes a lower drain portion of the second conductivity type underlying, continuous with, and more lightly doped than the main drain portion.

37. A structure as in claim 32 wherein:

the channel zone comprises part of a first well region situated in the semiconductor body and doped with semiconductor dopant of the first conductivity type having a concentration that locally reaches a maximum concentration in the first well region at a first subsurface maximum-concentration location extending generally laterally below the body'"'"'s upper surface;

the drain comprises a second well region doped with semiconductor dopant of the second conductivity type having a concentration that locally reaches a maximum concentration in the second well region at a second subsurface maximum-concentration location extending generally laterally below the body'"'"'s upper surface; and

a well-separating portion of the semiconductor body extends between the well regions and is more lightly doped than each well region such that the subsurface locations of the maximum concentrations of the well regions are spaced laterally apart from each other.

38. A structure as in claim 37 further including an electrically insulating region recessed into the semiconductor body along its upper surface and extending into second well region to laterally surround the main drain portion and laterally separate it from material of the second well region continuous with the well-separating portion, the gate electrode extending over the recessed insulating region partway to the main drain portion.

39. A structure as in claim 38 wherein the well-separating portion is of the first conductivity type and extends to the body'"'"'s upper surface whereby the channel zone includes at least part of the well-separating portion.

40. A structure as in claim 38 wherein the well-separating portion comprises a lower section of the first conductivity type and an upper section of the second conductivity type situated between the lower section and the gate dielectric layer such that the drain further includes the upper section of the well-separating portion.

43. A structure as in claim 32 wherein:

the transistor is a p-channel transistor; and

the source extension contains arsenic as semiconductor dopant of the second conductivity type.

44. A structure as in claim 32 wherein each contact includes a contact layer of a metal-semiconductor compound along each of the source and drain.

45. A structure as in claim 32 wherein:

the vertically extending portion of the source-side spacer comprises a first vertically extending layer and a second vertically extending layer chemically different from the first vertically extending layer such that the first vertically extending layer is situated between the gate electrode and the second vertically extending layer; and

the laterally extending portion of the source-side spacer comprises a first laterally extending layer and a second laterally extending layer chemically different from the first laterally extending layer such that the first laterally extending layer is situated between the gate electrode and the second laterally extending layer.

46. A structure as in claim 45 wherein:

the first layers of the source-side spacer comprise semiconductor oxide; and

the second layers of the source-side spacer comprise semiconductor nitride.

41. A structure as in claim A37 wherein all semiconductor dopant of the second conductivity type in the second well region has a concentration that decreases by at least a factor of 10 in moving upward from the second subsurface maximum-concentration location along a selected vertical location through the second well region to the gate dielectric layer, the second subsurface maximum-concentration location occurring no more than 10 times deeper below the gate dielectric layer than the maximum depth to which the source extends below the gate dielectric layer.

42. A structure as in claim 41 wherein all semiconductor dopant of the first conductivity type in the first well region has a concentration that decreases by at least a factor of 10 in moving upward from the first subsurface maximum-concentration location along a selected vertical location through the first well region to the gate dielectric layer, the first subsurface maximum-concentration location occurring no more than 10 times deeper below the gate dielectric layer than the maximum depth to which the source extends below the gate dielectric layer.