POWER SEMICONDUCTOR DEVICE STRUCTURE FOR INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF

• US 20100244125A1
• Filed: 03/26/2007
• Published: 09/30/2010
• Est. Priority Date: 03/28/2006
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Koops, Gerhard, Sonsky, Jan, Van Dalen, Rob
• Application Number:
  US12/294,820
• Publication Number:
  US 20100244125A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device comprises a conductive gate, provided in an upper part of a trench (11) formed in a semiconductor substrate (1), and a conductive field plate, extending in the trench, parallel to the conductive gate, to a depth greater that the conductive gate. The field plate is insulated from the walls and bottom of the trench by a field plate insulating layer that is thicker than the gate insulating layer. In one embodiment, the field plate is insulated within the trench from the gate. Impurity doped regions of a first conductivity type are provided at the surface of the substrate adjacent the first and second sides of the trench and form source and drain regions, and a body region (7) of second conductivity type is formed under the source region on the first side of the trench (11). The conductive gate is insulated from the body region (7) by a gate insulating layer. A method of making the semiconductor device is compatible with conventional CMOS processes.

Claims

1. A trench-gate semiconductor device comprising:

a semiconductor substrate having a first major surface;

a trench extending from the first major surface (3) into the substrate;

first and second impurity doped regions of a first conductivity type at respective first and second opposing sides of the trench adjacent the first major surface;

a body region of a second conductivity type, opposite to the first conductivity type, formed only below the first impurity doped region on the first side of the trench;

a drift region of the first conductivity type, below the body region and the second impurity doped region, the trench terminating in the drift region;

a conductive gate insulated from the body region by a gate insulator, and

a conductive field plate in the trench, the field plate extending into the trench parallel to the conductive gate to depth greater than or equal to the depth of the conductive gate, wherein the field plate is insulated from the drift region in the trench by a field plate insulating layer, and wherein the thickness of the field plate insulating layer is substantially greater than the thickness of the gate insulator.

2. A semiconductor device as claimed in claim 1, wherein the conductive gate is in an upper part of the trench adjacent the first side thereof, and the conductive field plate is adjacent to the conductive gate.

3. A semiconductor device as claimed in claim 1, wherein the thickness of the field plate insulating layer is in the range of about 50 to 800 nm.

4. A semiconductor device as claimed in claim 1, wherein the conductive gate extends to a depth from the first major surface that is substantially equal to the depth of the body region from the first major surface.

5. A semiconductor device as claimed in claim 1, wherein the second impurity doped region is spaced from the trench.

6. A semiconductor device as claimed in claim 5, wherein the second impurity doped region is spaced from the trench by a further trench filled with an insulating material, said further trench having a depth less than that of the trench.

7. A semiconductor device as claimed in any preceding claim, wherein the thickness of the field plate insulating layer on the second side of the trench is greater than on the first side of the trench.

8. A semiconductor device as claimed in claim 1, further comprising an auxiliary conductive gate adjacent, and insulated from, the body region at a side remote the conductive gate.

9. A method for making a semiconductor device, comprising:

forming a trench in a first major surface of a semiconductor substrate, the trench having first and second opposing sides;

lining the trench with a first insulating layer having a first thickness;

filling the trench with a conductive material;

forming first and second impurity doped regions of a first conductivity type adjacent the first major surface at the respective first and second sides of the trench;

forming a body region of a second conductivity type, opposite to the first conductivity type, only on the first side of the trench, the body region extending to a first predetermined depth from the first major surface.

forming a sub-trench extending to a second predetermined depth from the first major surface and having a first sidewall adjacent the body region;

lining the first sidewall of the sub-trench with a second insulating layer having a second thickness, which is substantially less that the first thickness, and

filling the sub-trench with a conductive material.

10. A method as claimed in claim 9, wherein the sub-trench is formed within the trench by removing a portion of the first insulating layer from only the first side of the trench, and wherein the first sidewall of the sub-trench is at the first side of the trench and a second sidewall is adjacent the conductive material.

11. A method as claimed in claim 9, wherein the second predetermined depth is substantially the same as the first predetermined depth.

12. A method as claimed in claim 9, wherein the step of forming the body region is performed before the step of forming the sub-trench.

13. A method for fabricating a power integrated circuit comprising a power device and at least one other semiconductor device, using the method as claimed in claim 9.