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Structure and Method for Forming a Salicide on the Gate Electrode of a Trench-Gate FET

  • US 20100244126A1
  • Filed: 03/27/2009
  • Published: 09/30/2010
  • Est. Priority Date: 03/27/2009
  • Status: Active Grant
First Claim
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1. A method of forming a trench-gate FET structure, the method comprising:

  • forming a plurality of trenches extending into a semiconductor region;

    forming a gate dielectric extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches;

    forming a gate electrode in each trench;

    forming well regions of a second conductivity type in the semiconductor region;

    forming source regions of the first conductivity type in upper portions of the well regions; and

    after forming the source regions, forming a salicide layer comprising at least one of cobalt or nickel over the gate electrode in each trench abutting portions of the gate dielectric, wherein the gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches.

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