Structure and Method for Forming a Salicide on the Gate Electrode of a Trench-Gate FET
First Claim
1. A method of forming a trench-gate FET structure, the method comprising:
- forming a plurality of trenches extending into a semiconductor region;
forming a gate dielectric extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches;
forming a gate electrode in each trench;
forming well regions of a second conductivity type in the semiconductor region;
forming source regions of the first conductivity type in upper portions of the well regions; and
after forming the source regions, forming a salicide layer comprising at least one of cobalt or nickel over the gate electrode in each trench abutting portions of the gate dielectric, wherein the gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches.
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Accused Products
Abstract
A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches. A gate electrode is formed in each trench isolated from the semiconductor region by the gate dielectric. Well regions of a second conductivity type are formed in the semiconductor region. Source regions of the first conductivity type are formed in upper portions of the well regions. After forming the source regions, a salicide layer is formed over the gate electrode in each trench abutting portions of the gate dielectric. The gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches.
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Citations
20 Claims
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1. A method of forming a trench-gate FET structure, the method comprising:
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forming a plurality of trenches extending into a semiconductor region; forming a gate dielectric extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches; forming a gate electrode in each trench; forming well regions of a second conductivity type in the semiconductor region; forming source regions of the first conductivity type in upper portions of the well regions; and after forming the source regions, forming a salicide layer comprising at least one of cobalt or nickel over the gate electrode in each trench abutting portions of the gate dielectric, wherein the gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of forming a trench-gate FET structure, the method comprising:
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forming a trench extending into the semiconductor region; forming a gate dielectric along sidewalls of the trench and over mesa surfaces of the semiconductor region adjacent to the trench; forming a gate electrode in the trench; performing a first implant of dopants of the first conductivity type into the semiconductor region; performing a second implant of dopants of a second conductivity type into the semiconductor region; performing one or more thermal processes to thereby form a source region corresponding to the first implant and a well region corresponding to the second implant, the one or more thermal processes being performed substantially without oxygen to minimize oxide formation over the gate electrode; and after performing the thermal process, forming a salicide layer comprising at least one of cobalt or nickel over the gate electrode abutting portions of the gate dielectric, wherein the gate dielectric prevents formation of the salicide layer along the mesa surfaces of the semiconductor region. - View Dependent Claims (11, 12, 13, 14)
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15. A trench-gate FET structure comprising:
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trenches extending into a semiconductor region, wherein portions of the semiconductor region extending between adjacent trenches form mesa surfaces; a continuous gate dielectric extending along sidewalls of each trench and over the mesa surfaces; a gate electrode in each trench; a salicide layer comprising at least one of cobalt or nickel extending over the gate electrode in each trench and abutting portions of the gate dielectric; a dielectric layer over the salicide layer in each trench; and an interconnect layer over the dielectric layer and over portions of the gate dielectric extending over the mesa surfaces. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification