Printed Dopant Layers

• US 20100244133A1
• Filed: 06/09/2010
• Published: 09/30/2010
• Est. Priority Date: 08/15/2006
• Status: Active Grant

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Patrick Smith, Zürcher, Fabio
• Inventors: KAMATH, Arvind, Rockenberger, Joerg, Smith, Patrick, Cleeves, James Montague, Zürcher, Fabio
• Granted Patent: US 8,304,780 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02288 printing, e.g. ink-jet printing per se B41J
• CPC Class Codes: H01L 21/02318 post-treatment
• CPC Class Codes: H01L 21/316 composed of oxides or glassy oxides or oxide based glass
• CPC Class Codes: H01L 21/3165 formed by oxidation H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

Claims

1. A method for making a MOS transistor, comprising the steps of:

a) forming a plurality of semiconductor islands by printing or coating a semiconductor ink on an electrically functional substrate;

b) printing a dielectric layer containing a dopant on or over the plurality of semiconductor islands; and

c) annealing the dielectric layer, the semiconductor islands and the substrate sufficiently to diffuse the dopant into the plurality of semiconductor islands.

2. The method of claim 1, wherein each of the semiconductor islands comprises a Group IVA element.

3. The method of claim 1, wherein forming the plurality of semiconductor islands comprises printing the semiconductor ink in a pattern, thereby forming an array of the semiconductor islands.

4. The method of claim 1, wherein the semiconductor ink comprises a silane in an amount of from 1 to 50 wt. % of the ink and a solvent in which the silane is soluble, the silane having a formula Si_xH_y, where x is from 3 to 1000, and y is from x to (2x+2), where x may be derived from an average number molecular weight of the silane.

5. The method of claim 1, further comprising forming gate dielectric layers on or over at least a subset of the plurality of semiconductor islands.

6. The method of claim 5, further comprising forming a gate on each of the gate dielectric layers, wherein forming the gates comprises printing a gate precursor ink on the gate dielectric layers.

7. The method of claim 6, wherein the gate precursor ink comprises metal nanoparticles and a solvent.

8. The method of claim 6, further comprising removing exposed portions of the gate dielectric layers after forming the gates and prior to printing the dielectric layer.

9. The method of claim 6, further comprising:

a) forming contact holes in the dielectric layer, exposing (i) at least part of an upper surface of one or more of the gates and (ii) portions of one or more of the semiconductor islands on opposed sides of each of the one or more gate(s); and

b) forming a metal layer in contact with (1) the upper surface(s) of each of the one or more gate(s) and (2) the portions of the one or more semiconductor islands, wherein forming the metal layer comprises printing a metal ink.

10. The method of claim 1, wherein printing the dielectric layer comprises inkjetting, flexographic printing, offset lithographic printing, gravure printing, or screen printing a doped dielectric ink formulation comprising a dielectric precursor, a dopant precursor, and a solvent.

11. The method of claim 1, wherein forming the plurality of semiconductor islands comprises curing the semiconductor ink after the semiconductor ink is printed or coated.

12. The method of claim 1, wherein the annealing is conducted at a temperature and for a length of time sufficient to form source/drain terminals in the semiconductor islands.

13. The method of claim 1, wherein forming the plurality of semiconductor islands comprises coating the semiconductor ink on the electrically functional substrate and patterning the coated semiconductor ink using low-resolution lithographic patterning.

14. An electronic device, comprising:

a) a substrate;

b) a plurality of physically isolated semiconductor islands on the substrate containing a diffusible dopant;

c) a doped dielectric layer in a pattern on or over the plurality of semiconductor islands and the substrate, the doped dielectric layer containing the diffusible dopant; and

d) a metal layer in electrical contact with the plurality of semiconductor islands.

15. The device of claim 14, wherein each of the semiconductor islands comprises a Group IVA element.

16. The device of claim 14, further comprising a gate dielectric layer on or over each of at least a subset of the plurality of semiconductor islands.

17. The device of claim 16, further comprising a gate over each of the subset of the plurality of semiconductor islands and on each of the gate dielectric layers, wherein the doped dielectric layer is over the gates.

18. The device of claim 17, further comprising contact holes in the doped dielectric layer, exposing (i) at least part of an upper surface of one or more the gates and (ii) portions of one or more of the semiconductor islands on opposed sides of each of the one or more gates.

19. The device of claim 18, wherein the metal layer is in contact with the exposed upper surface(s) of the one or more gate(s) and with the exposed portions of the one or more semiconductor islands.

20. The device of claim 17, wherein the gates comprise aluminum, silver, gold, copper, palladium, tungsten, platinum, or molybdenum.

21. The device of claim 14, wherein there are spaces between adjacent semiconductor islands and the doped dielectric layer is within the spaces between the adjacent semiconductor islands.

22. The device of claim 14, wherein the dielectric layer comprises a silicon oxide and a dopant selected from the group consisting of oxides and oxo compounds of phosphorous, boron, arsenic and antimony.