STRUCTURE AND METHOD FOR LATCHUP IMPROVEMENT USING THROUGH WAFER VIA LATCHUP GUARD RING

• US 20100244179A1
• Filed: 03/26/2009
• Published: 09/30/2010
• Est. Priority Date: 03/26/2009
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: VOLDMAN, Steven H.
• Granted Patent: US 7,989,282 B2
• Time in Patent Office: Days
• US Class Current: 257/496
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Abstract

A method and structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.

Claims

1. A method of manufacturing a semiconductor structure, comprising:

forming a latchup sensitive structure;

masking the latchup sensitive structure;

flipping the latchup sensitive structure and substrate to gain access to an underside thereof; and

etching a trough via through the substrate and adjacent the latchup sensitive structure using lithography and etching to isolate the latchup sensitive structure from at least an external source.

2. The method of claim 1, wherein the trough via is filled with a metal material, refractory material, an insulator, or a metal material with an insulator liner.

3. The method of claim 1, wherein the latchup sensitive structure is a P+ diffusion structure.

4. The method of claim 1, wherein the latchup sensitive structure is a CMOS structure.

5. The method of claim 1, wherein the latchup sensitive structure is a N+ diffusion structure.

6. The method of claim 1, wherein the latchup sensitive structure is bounded by the through wafer via to prevent parasitic carriers from being injected into the latchup sensitive structure.

7. The method of claim 1, wherein the through wafer via is etched to entirely surround the latchup sensitive structure.

8. A method of forming a structure, comprising:

forming at least a P+ diffusion structure that is sensitive to latchup; and

forming a guard ring structure bounding the P+ diffusion structure to isolate the P+ diffusion structure from external sources.

9. The method of claim 8, wherein the guard ring structure completely surrounds the P+ diffusion structure and is filled with metal, refractory material, an insulator or a metal lined with an insulator.

10. The method of claim 8, further comprising forming at least a N−

diffusion structure that is sensitive to latchup and which is bounded by the guard ring structure.

11. A structure, comprising:

a latchup sensitive structure; and

a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.

12. The structure of claim 11, wherein the latchup sensitive structure is a P+ diffusion structure.

13. The structure of claim 11, wherein the latchup sensitive structure is a CMOS structure.

14. The structure of claim 11, wherein the latchup sensitive structure is an N+ diffusion structure.

15. The structure of claim 11, wherein the through wafer via isolates the latchup sensitive structure from an external source.

16. The structure of claim 11, wherein the through wafer via is filled with one of:

a refractory material, a metal, an insulator and a metal material lined with an insulator.

17. The structure of claim 11, wherein the through wafer via completely surrounds the latchup sensitive structure.

18. The structure of claim 11, wherein the through wafer via partially surrounds the latchup sensitive structure.

19. The structure of claim 11, wherein the through wafer via is a guard ring structure that prevents latchup resulting from a minority injection source.

20. A structure comprising:

a latchup sensitive structure; and

a guard ring that bounds the latchup sensitive structure to isolate the latchup sensitive structure from an external source.

21. The structure of claim 20, wherein the latchup sensitive structure is one of a CMOS, PMOS and NMOS device.

22. The structure of claim 20, wherein the guard ring is one of a metal material, a refractory material, an insulator, a metal lined with an insulator or devoid of material.

23. The structure of claim 20, wherein the guard ring completely surrounds the latchup sensitive structure.

24. The structure of claim 20, wherein the guard ring is structured to protect the latchup sensitive structure from a high voltage external source.

25. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising a latchup sensitive structure, and a guard ring that bounds the latchup sensitive structure to isolate the latchup sensitive structure from an external source.