VIA STRUCTURE AND VIA ETCHING PROCESS OF FORMING THE SAME

• US 20100244247A1
• Filed: 03/12/2010
• Published: 09/30/2010
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHIOU, Wen-Chih, YU, Chen-Hua, CHANG, Hung-Pin
• Granted Patent: US 8,329,578 B2
• Time in Patent Office: Days
• US Class Current: 257/741
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A via etching process forms a through-substrate via having a round corner and a tapered sidewall profile. A method includes providing a semiconductor substrate; forming a hard mask layer and a patterned photoresist layer on the semiconductor substrate; forming an opening in the hard mask and exposing a portion of the semiconductor substrate; forming a via passing through at least a part of the of semiconductor substrate using the patterned photoresist layer and hard mask layer as a masking element; performing a trimming process to round the top corner of the via; and removing the photoresist layer.

Claims

1. A method, comprising:

providing a semiconductor substrate;

forming a hard mask layer on the semiconductor substrate;

forming a photoresist layer on the hard mask layer;

patterning the photoresist layer to form a first opening;

patterning the hard mask layer to form a second opening underlying the first opening, exposing a portion of the semiconductor substrate;

etching the exposed portion of the semiconductor substrate to form a via passing through at least a part of the semiconductor substrate;

performing a trimming process to round the top corner of the via; and

removing the photoresist layer.

2. The method of claim 1, further comprising:

forming a device formed on the semiconductor substrate before forming a hard mask layer on the semiconductor substrate; and

forming a contact structure in the hard mask layer after forming a hard mask layer on the semiconductor substrate;

wherein the contact structure electrically connects to the device.

3. The method of claim 1, wherein the hard mask layer comprises an etch stop layer and a dielectric layer.

4. The method of claim 1, wherein the trimming process reduces the roughness of the via sidewall.

5. The method of claim 1, wherein the trimming process forms the via with a tapered sidewall profile.

6. The method of claim 1, wherein the trimming process uses a mixed gas comprising one or more of He, Ar, O₂, CF based gases, NF₃ or SF₆.

7. The method of claim 1, further comprising forming a conductive layer in the via after removing the photoresist layer.

8. A method, comprising:

providing a semiconductor substrate comprising a hard mask layer formed thereon;

forming an interconnect structure in the hard mask layer;

forming a photoresist layer on the hard mask layer;

patterning the photoresist layer to form a first opening;

patterning the hard mask layer to form a second opening underlying the first opening, exposing a portion of the semiconductor substrate;

etching the exposed portion of the semiconductor substrate to form a via passing through at least a part of the semiconductor substrate;

performing a trimming process to round the top corner of the via; and

removing the photoresist layer.

9. The method of claim 8, wherein the hard mask layer further comprises an etch stop layer formed on the semiconductor substrate, a first dielectric layer formed on the etch stop layer, and a second dielectric layer formed on the first dielectric layer, wherein a contact structure is formed in the etch stop layer and the first dielectric layer;

and wherein the interconnect structure is formed in the second dielectric layer and electrically connected to the contact structure.

10. The method of claim 8, wherein the trimming process reduces the roughness of the via sidewall.

11. The method of claim 8, wherein the trimming process forms the via with a tapered sidewall profile.

12. The method of claim 8, wherein the trimming process uses a mixed gas comprising one or more of He, Ar, O₂, CF based gases, NF₃ or SF₆.

13. An integrated circuit structure, comprising:

a semiconductor substrate;

a hard mask layer formed on the semiconductor substrate;

at least a conductive layer formed in the hard mask layer; and

a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall.

14. The integrated circuit structure of claim 13, wherein the hard mask layer comprises:

an etch stop layer formed on the semiconductor substrate; and

a first dielectric layer formed on the etch stop layer;

wherein the conductive layer formed in the hard mask layer is a contact structure.

15. The integrated circuit structure of claim 13, wherein the hard mask layer comprises:

an etch stop layer formed on the semiconductor substrate;

a first dielectric layer formed on the etch stop layer; and

a second dielectric layer formed on the first dielectric layer;

wherein the conductive layer formed in the hard mask layer is an interconnect structure.

16. The integrated circuit structure of claim 13, wherein the via is filled with a conductive material.

17. The integrated circuit structure of claim 16, wherein the via is filled with copper.

18. The integrated circuit structure of claim 14, wherein the etch stop layer comprises silicon nitride.