WIRING BOARD

• US 20100244274A1
• Filed: 03/19/2010
• Published: 09/30/2010
• Est. Priority Date: 03/27/2009
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Akahoshi, Tomoyuki, ISHITSUKA, Takeshi
• Application Number:
  US12/727,617
• Publication Number:
  US 20100244274A1
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 2201/09236 Parallel layout layout of balanced signal pairs H05K1/0245; superposed layout H05K2201/09672
• CPC Class Codes: H05K 2201/09672 Superposed layout, i.e. in different planes parallel traces in one plane H05K2201/09236
• CPC Class Codes: H05K 2201/098 Special shape of the cross-section of conductors, e.g. very thick plated conductors

Abstract

A wiring board includes a first conductor constituting a signal line, a second conductor constituting a ground conductor or a power conductor, a dielectric layer disposed between and separately the first and second conductors, and a third conductor arranged between the first and second conductor, the third conductor being connected to the second conductor, and having a width narrower than that of the first conductor, the third conductor entirely opposing the first conductor, the entire portion of the third conductor being covered by the first conductor.

Claims

1. A wiring board comprising:

a first conductor constituting a signal line;

a second conductor constituting a ground conductor or a power conductor;

a dielectric layer disposed between and separately the first and second conductors; and

a third conductor arranged between the first and second conductor, the third conductor being connected to the second conductor, and having a width narrower than that of the first conductor, the third conductor entirely opposing the first conductor, the entire portion of the third conductor being covered by the first conductor.

2. The wiring board according to claim 1, wherein the third conductor is connected to the second conductor and a plurality of via-conductors for interlayer connection.

3. The wiring board according to claim 1, further comprising a fourth conductor formed between the third and second conductor, the third conductor having a width narrower than that of the third conductor, the fourth conductor connected to a surface of the third and second conductors.

4. The wiring board according to claim 3, wherein the third and fourth conductor extends in a direction parallel with each other, the third and fourth conductors being aligned to a center line of the line width of the first conductor, and the center lines of the third and fourth conductors along the direction are aligned with each other.

5. The wiring board according to claim 3, wherein the dielectric layer is made of a silicon oxide or an organic compound.

6. A semiconductor device comprising:

a semiconductor chip having a connecting terminal;

a wiring board having a connector being connected to the connecting terminal of the semiconductor chip, the wiring board including;

a first conductor constituting a signal line;

a second conductor constituting a ground conductor or a power conductor;

a dielectric layer disposed between and separately the first and second conductors; and

a third conductor arranged between the first and second conductor, the third conductor being connected to the second conductor, and having a width narrower than that of the first conductor, the third conductor entirely opposing the first conductor, the entire portion of the third conductor being covered by the first conductor.

7. The semiconductor device according to claim 6, wherein the third conductor is connected to the second conductor and a plurality of via-conductors for interlayer connection.

8. The semiconductor device according to claim 6, further comprising a fourth conductor formed between the third and second conductor, the third conductor having a width narrower than that of the third conductor, the fourth conductor connected to a surface of the third and the second conductors.

9. The semiconductor device according to claim 8, wherein the third and fourth conductor extends in a direction parallel with each other, the third and fourth conductors being aligned to a center line of the line width of the first conductor, and the center lines of the third and fourth conductors along the direction are aligned with each other.

10. The semiconductor device according to claim 8, wherein the dielectric layer is made of a silicon oxide or an organic compound.

11. A semiconductor device comprising:

a plurality of semiconductor chips having a connecting terminal;

a wiring board having a connector being connected to the connecting terminal of the semiconductor chip, the wiring board including;

a first conductor constituting a signal line;

a second conductor constituting a ground conductor or a power conductor;

a dielectric layer disposed between and separately the first and second conductors; and

a third conductor arranged between the first and second conductor, the third conductor being connected to the second conductor, and having a width narrower than that of the first conductor, the third conductor entirely opposing the first conductor, the entire portion of the third conductor being covered by the first conductor;

wherein the plurality of semiconductor devices are connected to the first conductive layer, and the plurality of semiconductor devices are respectively connected via the first conductive layer.

12. The semiconductor device according to claim 11, wherein the third conductor is connected to the second conductor and a plurality of via-conductors for interlayer connection.

13. The semiconductor device according to claim 11, further comprising a fourth conductor formed between the third and second conductor, the third conductor having a width narrower than that of the third conductor, the fourth conductor connected to a surface of the third and the second conductors.

14. The semiconductor device according to claim 13, wherein the third and fourth conductor extends in a direction parallel with each other, the third and fourth conductors being aligned to a center line of the line width of the first conductor, and the center lines of the third and fourth conductors along the direction are aligned with each other.

15. The semiconductor device according to claim 13, wherein the dielectric layer is made of a silicon oxide or an organic compound.