METHOD FOR ULTRA THIN WAFER HANDLING AND PROCESSING

• US 20100244284A1
• Filed: 03/25/2010
• Published: 09/30/2010
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WANG, Tsung-Ding, WU, Weng-Jin, CHIOU, Wen-Chih, YANG, Ku-Feng
• Granted Patent: US 8,232,140 B2
• Time in Patent Office: Days
• US Class Current: 257/787
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/80006 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/80894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/95001 : involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1421 : RF devices
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A method for thin wafer handling and processing is provided. In one embodiment, the method comprises providing a wafer having a plurality of semiconductor chips, the wafer having a first side and a second side. A plurality of dies are attached to the first side of the wafer, at least one of the dies are bonded to at least one of the plurality of semiconductor chips. A wafer carrier is provided, wherein the wafer carrier is attached to the second side of the wafer. The first side of the wafer and the plurality of dies are encapsulated with a planar support layer. A first adhesion tape is attached to the planar support layer. The wafer carrier is then removed from the wafer and the wafer is diced into individual semiconductor packages.

Claims

1. A method for thin wafer handling and processing, comprising:

providing a wafer having a plurality of semiconductor chips, the wafer having a first side and a second side;

attaching a plurality of dies to the first side of the wafer, wherein at least one of the dies bonded to at least one of the plurality of semiconductor chips;

providing a wafer carrier, wherein the wafer carrier is attached to the second side of the wafer;

encapsulating the first side of the wafer and the plurality of dies with a planar support layer; and

attaching a first adhesion tape to the planar support layer.

2. The method of claim 1, wherein the wafer carrier comprises a silicon substrate, glass substrate, polymer substrate, polymer-based composite substrate, or thick tape.

3. The method of claim 1, wherein the wafer carrier is attached to the second side of the wafer by a method selected from the group consisting of adhesive bonding, tape bonding, and resin bonding.

4. The method of claim 1, wherein attaching a plurality of dies to the first side of the wafer is performed by a method selected from the group consisting of die bonding, solder bumping, oxide-to-oxide bonding, oxide-to-silicon bonding, copper-to-copper bonding, adhesive bonding, fusion bonding via oxide-to-oxide bonding, and bonding by a glue medium such as benzocyclobutene (BCB).

5. The method of claim 1, wherein the support layer comprises PEG (polyethylene glycol), wax, polymer, or polymer-based material.

6. The method of claim 1, wherein encapsulating the first side of the wafer and the plurality of dies with the support layer comprises spin coating or printing.

7. The method of claim 1, wherein the first adhesion tape comprises a dicing tape or an ultraviolet tape.

8. The method of claim 1, further comprising removing the wafer carrier from the wafer and dicing the wafer into individual semiconductor packages.

9. The method of claim 8, further comprising attaching a second adhesion tape to the second side of the wafer, removing the first adhesion tape, removing the support layer, and removing the second adhesion tape.

10. The method of claim 9, wherein the second adhesion tape comprises a dicing tape or an ultraviolet tape.

11. The method of claim 1, further comprising removing the wafer carrier from the wafer and attaching a second adhesion tape to the second side of the wafer.

12. The method of claim 11, wherein the second adhesion tape comprises a dicing tape or an ultraviolet tape.

13. The method of claim 11, further comprising removing the first adhesion tape, removing the support layer, and dicing the wafer into individual semiconductor packages.

14. A product for thin wafer handling and processing, the product made by the method of claim 8.

15. A product for thin wafer handling and processing, the product made by the method of claim 13.