UNDER-VOLTAGE AND OVER-VOLTAGE DETECTION CIRCUIT AND DRIVING METHOD THEREOF

• US 20100244885A1
• Filed: 03/16/2010
• Published: 09/30/2010
• Est. Priority Date: 03/24/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Inventors: LEE, Byongsung, LEE, Kyoungmin, KIM, Juho, KWON, Duckki, KANG, Eunchul
• Granted Patent: US 8,410,809 B2
• Time in Patent Office: Days
• US Class Current: 324/764.10
• CPC Class Codes: G01R 19/16523 using diodes, e.g. Zener diodes

Abstract

The present invention relates to a low-voltage and over-voltage detection circuit and a driving method thereof.

The low-voltage and over-voltage detection circuit according to the present invention receives a power source voltage, generates a shift voltage by shifting the received voltage to a predetermined level, and fixes the shift voltage as a clamping voltage when the shift voltage is higher than a predetermined clamping voltage. The low-voltage and over-voltage detection circuit according to the present invention includes a first transistor and a second transistor. The first transistor generates a regulator voltage that varies according to the power source voltage and performs a switching operation according to the shift voltage and the regulator voltage, and the second transistor is connected in parallel with the first transistor and generates hysteresis. The low-voltage and over-voltage detection circuit according to the present invention determines whether the power source voltage is a low-voltage or an over-voltage by using a drain voltage generated according to currents flowing to the first and second transistors.

Claims

1. A low-voltage and over-voltage detection circuit comprising:

a level shifter receiving a power source voltage and shifting an input voltage to a predetermined level to generate a shift voltage;

a voltage clamper maintaining the shift voltage at a clamping voltage when the shift voltage is higher than a predetermined clamping voltage;

a voltage regulator generating a regulator voltage that varies according to the power source voltage; and

a voltage detector receiving the shift voltage and the regulator voltage, including first and second transistors, and determining whether the power source voltage is a low-voltage or an over-voltage by using a drain voltage generated according to currents flowing to the first and second transistors, the first transistor performing a switching operation according to the two input voltages and the second transistor connected to the first transistor in parallel and generating hysteresis.

2. The low-voltage and over-voltage detection circuit of claim 1, wherein the voltage detector comprises a driver receiving the drain voltage, determining the power source voltage to be included in a normal range when the drain voltage is close to the regulator voltage and generating a first-level detection signal, and determining the power source voltage as a low-voltage or an over-voltage when the drain voltage is close to the power source voltage and generating a second-level detection signal.

3. The low-voltage and over-voltage detection circuit of claim 2, wherein the first transistor has a gate electrode to which the shift voltage is input and a source electrode to which the regulator voltage is input, and the second transistor has a source electrode to which the regulator voltage is input and a gate electrode to which a reverse detection signal that is opposite to the detection signal is input.

4. The low-voltage and over-voltage detection circuit of claim 3, wherein the first and second transistors are n-channel type transistors.

5. The low-voltage and over-voltage detection circuit of claim 1, wherein the level shifter comprises:

a first current source having a first end to which the power source voltage is input, and generating a constant first current; and

a third transistor being diode-connected and flowing the constant current thereto.

6. The low-voltage and over-voltage detection circuit of claim 5, wherein the voltage clamper comprises:

a Zener diode row having a first end to which the shift voltage is applied; and

a second current source connected in parallel with the Zener diode row, and providing a path for the first current before the Zener diode row is turned on.

7. The low-voltage and over-voltage detection circuit of claim 1, wherein the voltage regulator comprises:

a first current source having a first end to which the power source voltage is applied, and generating a constant current;

a first Zener diode having a cathode to which the power source voltage is input;

a second current source connected to an anode of the first Zener diode; and

a third transistor having a gate electrode connected to the anode of the first Zener diode and a source electrode to which the current of the first current source is supplied, a voltage at the source electrode of the third transistor being equivalent to the regulator voltage.

8. The low-voltage and over-voltage detection circuit of claim 7, wherein the voltage detector comprises a driver supplied with the power source voltage and the regulator voltage, receiving the drain voltage, determining the power source voltage to be included in a normal range when the drain voltage is close to the regulator voltage and generating a first-level detection signal, and determining the power source voltage to be a low-voltage or an over-voltage when the drain voltage is close to the power source voltage and generating a second-level detection signal.

9. The low-voltage and over-voltage detection circuit of claim 8, wherein the first transistor has a gate electrode to which the shift voltage is input and a source electrode connected to a source electrode of the third electrode, and the second transistor has a gate electrode to which a reverse detection signal that is opposite to the detection signal is input and a source electrode connected to the source electrode of the third transistor.

10. The low-voltage and over-voltage detection circuit of claim 1, wherein the regulator voltage sequentially comprises, when the power source voltage is increased:

a first period during which the regulator voltage is linearly increased or decreased according to the power source voltage;

a second period during which the regulator voltage is maintained at a constant level; and

a third period during which the regulator voltage is linearly increased or decreased according to the power source voltage, and

when the power source voltage is decreased, the regulator voltage sequentially includes the third period, the second period, and the first period.

11. The low-voltage and over-voltage detection circuit of claim 1, wherein the shift voltage sequentially comprises, when the power source voltage is increased:

a first period during which the shift voltage is maintained at a ground voltage;

a second period during which the shift voltage is linearly increased or decreased; and

a third period during which the shift voltage is constantly maintained at the clamping voltage, and

when the power source voltage is decreased, the shift voltage sequentially includes the third period, the second period, and the first period.

12. A driving method of a low-voltage and over-voltage detection circuit including a first transistor and a second transistor connected in parallel with the first transistor, comprising:

receiving a power source voltage and generating a shift voltage by shifting the power source voltage to a predetermined level;

when the shift voltage is higher than a predetermined clamping voltage, fixing the shift voltage as a clamping voltage;

generating a regulator voltage that varies according to the power source voltage;

switching the first transistor according to the shift voltage and the regulator voltage;

determining the power source voltage to be included in a normal range when drain voltages of the first and second transistors are close to the regulator voltage and generating a first-level detection signal, and determining the power source voltage to be a low-voltage or an over-voltage when the drain voltages are close to the power source voltage and generating a second-level detection signal; and

switching the second transistor according to a reverse detection signal that is opposite to the detection signal.

13. The driving method of claim 12, wherein the switching the first transistor comprises:

inputting the shift voltage to a gate electrode of the first transistor; and

inputting the regulator voltage to a source electrode of the first transistor.

14. The driving method of claim 12, wherein the switching the second transistor comprises:

inputting the reverse detection signal to a gate electrode of the second transistor; and

inputting the regulator voltage to a source electrode of the second transistor.

15. The driving method of claim 12, wherein the regulator voltage sequentially comprises, when the power source voltage is increased:

a first period during which the regulator voltage is linearly increased or decreased according to the power source voltage;

a second period during which the regulator voltage is maintained at a constant level; and

a third period during which the regulator voltage is linearly increased or decreased according to the power source voltage, and

when the power source voltage is decreased, the regulator voltage sequentially comprises the third period, the second period, and the first period.

16. The driving method of claim 12, wherein the shift voltage sequentially comprises, when the power source voltage is increased:

a first period during which the shift voltage is maintained at a ground voltage;

a second period during which the shift voltage is linearly increased or decreased; and

a third period during which the shift voltage is constantly maintained at the clamping voltage, and

when the power source voltage is decreased, the shift voltage sequentially comprises the third period, the second period, and the first period.