TIME-TO-DIGITAL CONVERTER (TDC) WITH IMPROVED RESOLUTION

• US 20100244971A1
• Filed: 05/06/2009
• Published: 09/30/2010
• Est. Priority Date: 03/30/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Wang, Kevin H., Palakurty, Saru, Bossu, Frederic
• Granted Patent: US 8,098,085 B2
• Time in Patent Office: Days
• US Class Current: 331/1.A
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60

Abstract

A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.

Claims

1. An apparatus comprising:

a first delay path configured to receive a first input signal and a first reference signal and to provide a first output indicative of a phase difference between the first input signal and the first reference signal;

a second delay path configured to receive a second input signal and a second reference signal and to provide a second output indicative of a phase difference between the second input signal and the second reference signal; and

a delay unit configured to delay the second input signal relative to the first input signal or to delay the second reference signal relative to the first reference signal.

2. The apparatus of claim 1, wherein the delay unit is configured to receive the first reference signal and to provide a delayed first reference signal as the second reference signal, and wherein the second delay path is configured to receive the first input signal as the second input signal.

3. The apparatus of claim 1, wherein the delay unit is configured to receive the first input signal and to provide a delayed first input signal as the second input signal, and wherein the second delay path is configured to receive the first reference signal as the second reference signal.

4. The apparatus of claim 1, wherein the delay unit is configured to receive a reference signal, to provide the reference signal delayed by a first amount as the first reference signal, and to provide the reference signal delayed by a second amount as the second reference signal.

5. The apparatus of claim 1, wherein the delay unit is configured to delay the second reference signal by one half inverter delay relative to the first reference signal.

6. The apparatus of claim 1, wherein the delay unit comprises

a first delay block configured to provide a fixed delay for the first input signal or the first reference signal and to provide a variable delay for the second input signal or the second reference signal.

7. The apparatus of claim 6, wherein the delay unit further comprises

a second delay block coupled to the first delay block and configured to provide a variable delay for the first input signal or the first reference signal and to provide a fixed delay for the second input signal or the second reference signal.

8. The apparatus of claim 1, wherein the delay unit comprises

a plurality of delay cells coupled in parallel, each delay cell comprising a first signal path and a second signal path, wherein first signal paths for the plurality of delay cells provide equal delay, wherein second signal paths for the plurality of delay cells provide different delays, and wherein one of the plurality of delay cells is selected to delay the second input signal relative to the first input signal or to delay the second reference signal relative to the first reference signal.

9. The apparatus of claim 1, wherein the first delay path comprises

a first set of inverters coupled in series and configured to receive the first input signal, and

a set of flip-flops coupled to the first set of inverters and configured to receive the first reference signal and provide a set of output signals for the first output.

10. The apparatus of claim 9, wherein the first delay path further comprises

a second set of inverters coupled in series and configured to receive an inverted first input signal, and wherein the set of flip-flops is further coupled to the second set of inverters, each flip-flop receiving a respective differential input signal from the first and second sets of inverters.

11. The apparatus of claim 1, further comprising:

a phase computation unit configured to receive the first and second outputs from the first and second delay paths and to provide a phase difference between an input signal and a reference signal, wherein the first and second input signals are derived based on the input signal, and wherein the first and second reference signals are derived based on the reference signal.

12. The apparatus of claim 11, wherein the first and second outputs from the first and second delay paths have a resolution of one inverter delay, and wherein the phase difference from the phase computation unit has a resolution of less than one inverter delay.

13. An apparatus comprising:

a digital phase locked loop (DPLL) comprising

a time-to-digital converter (TDC) configured to receive an input signal and a reference signal and to provide a phase difference between the input signal and the reference signal, the phase difference having a resolution of less than one inverter delay, and

a loop filter configured to receive an error signal derived based on the phase difference from the TDC and to provide a control signal for an oscillator.

14. The apparatus of claim 13, wherein the TDC comprises

a first delay path configured to receive a first input signal and a first reference signal and to provide a first output indicative of a phase difference between the first input signal and the first reference signal,

a second delay path configured to receive a second input signal and a second reference signal and to provide a second output indicative of a phase difference between the second input signal and the second reference signal,

a delay unit configured to delay the second input signal relative to the first input signal or to delay the second reference signal relative to the first reference signal, and

a phase computation unit configured to receive the first and second outputs from the first and second delay paths and to provide the phase difference between the input signal and the reference signal, wherein the first and second input signals are derived based on the input signal, and wherein the first and second reference signals are derived based on the reference signal.

15. The apparatus of claim 13, wherein the DPLL further comprises

an accumulator configured to receive an oscillator signal from the oscillator and to provide a coarse phase difference having a resolution of one oscillator signal cycle, and wherein the error signal is derived based further on the coarse phase difference.

16. The apparatus of claim 13, wherein the DPLL further comprises

a signal multiplexer configured to receive a clock signal and a feedback signal derived based on an oscillator signal from the oscillator, to provide one of the feedback signal and the clock signal as the input signal to the TDC, and to provide the other one of the feedback signal and the clock signal as the reference signal to the TDC.

17. A wireless device comprising:

a master oscillator configured to generate a master clock having a fixed frequency; and

a digital phase locked loop (DPLL) configured to receive the master clock and provide an oscillator signal having a configurable frequency determined based on the fixed frequency of the master clock, the DPLL comprising a time-to-digital converter (TDC) configured to receive an input signal and a reference signal and to provide a phase difference between the input signal and the reference signal, the input signal or the reference signal being derived based on the master clock, and the phase difference having a resolution of less than one inverter delay.

18. The wireless device of claim 17, further comprising:

a receiver configured to receive and downconvert a received signal with the oscillator signal from the DPLL.

19. The wireless device of claim 17, further comprising:

a transmitter configured to receive and upconvert a baseband signal with the oscillator signal from the DPLL.

20. A method of operating a time-to-digital converter (TDC) comprising first and second delay paths, the method comprising:

generating a first output indicative of a phase difference between a first input signal and a first reference signal for the first delay path of the TDC;

generating a second output indicative of a phase difference between a second input signal and a second reference signal for the second delay path of the TDC; and

delaying the second input signal relative to the first input signal or delaying the second reference signal relative to the first reference signal.

21. The method of claim 20, wherein the delaying comprises

delaying the second reference signal by one half inverter delay relative to the first reference signal.

22. The method of claim 20, wherein the delaying comprises

delaying the first reference signal by a first amount and delaying the second reference signal by a second amount to time align the first and second reference signals, and

further delaying the second reference signal by one half inverter delay relative to the first reference signal.

23. The method of claim 20, wherein the generating the first output comprises

delaying the first input signal by different amounts to obtain a set of delayed input signals, and

latching the set of delayed input signals with the first reference signal to obtain a set of output signals for the first output.

24. The method of claim 20, further comprising:

determining a phase difference between an input signal and a reference signal based on the first and second outputs, wherein the first and second input signals are derived based on the input signal, and wherein the first and second reference signals are derived based on the reference signal.

25. The apparatus of claim 24, wherein the first and second outputs have a resolution of one inverter delay, and wherein the phase difference between the input signal and the reference signal has a resolution of less than one inverter delay.

26. An apparatus comprising:

means for generating a first output indicative of a phase difference between a first input signal and a first reference signal for a first delay path of a time-to-digital converter (TDC);

means for generating a second output indicative of a phase difference between a second input signal and a second reference signal for a second delay path of the TDC; and

means for delaying the second input signal relative to the first input signal or delaying the second reference signal relative to the first reference signal.

27. The apparatus of claim 26, wherein the means for delaying comprises

means for delaying the second reference signal by one half inverter delay relative to the first reference signal.

28. The apparatus of claim 26, further comprising:

means for determining a phase difference between an input signal and a reference signal based on the first and second outputs, wherein the first and second input signals are derived based on the input signal, and wherein the first and second reference signals are derived based on the reference signal.

29. The apparatus of claim 28, wherein the first and second outputs have a resolution of one inverter delay, and wherein the phase difference between the input signal and the reference signal has a resolution of less than one inverter delay.

30. A method of calibrating a time-to-digital converter (TDC) comprising first and second delay paths, the method comprising:

adjusting delay of a first reference signal for the first delay path to time align the first reference signal with a first input signal for the first delay path; and

adjusting delay of a second reference signal for the second delay path to time align the second reference signal with a second input signal for the second delay path.

31. The method of claim 30, wherein the delay of each of the first and second reference signals is adjusted in increments of less than one inverter delay.

32. The method of claim 30, further comprising:

further adjusting the delay of the second reference signal to obtain one additional inverter delay for the second reference signal;

determining one half inverter delay for the second reference signal based on the delay to time align the second reference signal with the second input signal and the delay to obtain one additional inverter delay for the second reference signal; and

configuring the TDC to delay the second reference signal by one half inverter delay relative to the first reference signal.

33. The method of claim 32, wherein the adjusting the delay of the second reference signal comprises

receiving N output signals from the second delay path, where N is greater than one,

identifying L consecutive output signals, starting with a first output signal, having a first logic value, where L is one or greater, and

adjusting the delay of the second reference signal until an (L+1)-th output signal toggles from a second logic value to the first logic value.

34. The method of claim 33, wherein the further adjusting the delay of the second reference signal comprises

further adjusting the delay of the second reference signal until an (L+2)-th output signal toggles from the second logic value to the first logic value.

35. An apparatus comprising:

means for adjusting delay of a first reference signal for a first delay path of a time-to-digital converter (TDC) to time align the first reference signal with a first input signal for the first delay path; and

means for adjusting delay of a second reference signal for a second delay path of the TDC to time align the second reference signal with a second input signal for the second delay path.

36. The apparatus of claim 35, further comprising:

means for further adjusting the delay of the second reference signal to obtain one additional inverter delay for the second reference signal;

means for determining one half inverter delay for the second reference signal based on the delay to time align the second reference signal with the second input signal and the delay to obtain one additional inverter delay for the second reference signal; and

means for configuring the TDC to delay the second reference signal by one half inverter delay relative to the first reference signal.

37. The apparatus of claim 36, wherein the means for adjusting the delay of the second reference signal comprises

means for receiving N output signals from the second delay path, where N is greater than one,

means for identifying L consecutive output signals, starting with a first output signal, having a first logic value, where L is one or greater, and

means for adjusting the delay of the second reference signal until an (L+1)-th output signal toggles from a second logic value to the first logic value.

38. The apparatus of claim 37, wherein the means for further adjusting the delay of the second reference signal comprises

means for further adjusting the delay of the second reference signal until an (L+2)-th output signal toggles from the second logic value to the first logic value.

39. A computer program product, comprising:

a computer-readable medium comprising;

code for causing at least one computer to adjust delay of a first reference signal for a first delay path of a time-to-digital converter (TDC) to time align the first reference signal with a first input signal for the first delay path,

code for causing the at least one computer to adjust delay of a second reference signal for a second delay path of the TDC to time align the second reference signal with a second input signal for the second delay path,

code for causing the at least one computer to further adjust the delay of the second reference signal to obtain one additional inverter delay for the second reference signal,

code for causing the at least one computer to determine one half inverter delay for the second reference signal based on the delay to time align the second reference signal with the second input signal and the delay to obtain one additional inverter delay for the second reference signal, and

code for causing the at least one computer to configure the TDC to delay the second reference signal by one half inverter delay relative to the first reference signal.