Clock Spreading Systems and Methods

• US 20100244976A1
• Filed: 03/31/2009
• Published: 09/30/2010
• Est. Priority Date: 03/31/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kerr, Jeff, Fresquez, Jose, Feygin, Gennady
• Granted Patent: US 7,944,319 B2
• Time in Patent Office: Days
• US Class Current: 332/144
• CPC Class Codes: H03K 7/06 Frequency or rate modulation, i.e. PFM or PRM
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 2215/067 by modulation dispersion

Abstract

Clock spreading systems and methods are disclosed. In one embodiment of the invention, a clock spreading system is provided in an integrated transceiver system that comprises a base band control system and a transceiver coupled to the base band control system. The clock spreading system provides a spread clock output signal derived from a clock reference signal for clocking one of the base band control system and the transceiver. The clock spreading system is configured to provide a periodic phase modulated spread clock output signal during receiving of data in a receive mode and a pseudo-random phase modulated spread clock output signal during transmitting of data in a transmit mode.

Claims

1. An integrated transceiver system comprising:

a base band control system;

a transceiver coupled to the base band control system; and

a clock spreading system that provides a spread clock output signal derived from a clock reference signal for clocking one of the base band control system and the transceiver, the clock spreading system being configured to provide a periodic phase modulated spread clock output signal during receiving of data in a receive mode and a pseudo-random phase modulated spread clock output signal during transmitting of data in a transmit mode.

2. The system of claim 1, wherein the clock spreading system employs a triangular modulation for the modulation of both the periodic phase modulated spread clock output signal and the pseudo-random phase modulated spread clock output signal.

3. The system of claim 2, wherein the clock spreading system employs the triangular modulation by sequentially selecting between a plurality of phase delay offset clock signals sequentially spaced apart in predetermined phase delay offset increments in increasing increments from a zero phase delay offset to a maximum phase delay offset and sequentially selecting between the plurality of phase delay offset clock signals in decreasing increments from the maximum phase delay offset to the zero phase delay offset.

4. The system of claim 3, wherein the clock spreading system continuously repeats the triangular modulation and is configured to hold the spread clock output signal at the zero phase delay offset and the maximum phase delay offset for a pseudo-random period of time in the transmit mode and to hold the spread clock output signal at the zero phase delay offset and the maximum phase delay offset for a predetermined period of time in the receive mode.

5. The system of claim 4, wherein the spread clock output signal has a frequency that is lower than a reference frequency of the clock reference signal during the increasing increments and a frequency that is higher than the reference frequency during the decreasing increments.

6. The system of claim 1, wherein the clock spreading system employs self-timing such that the spread clock output signal clocks components of the clock spreading system.

7. The system of claim 1, wherein the clock spreading system comprises:

a delay line logic device that receives a clock reference signal and provides a plurality of phase delay offset clock signals sequentially spaced apart in predetermined phase delay offset increments;

a plurality of clock gating latches with a given latch receiving a respective phase delay offset clock signal for each of the plurality of phase delay offset clock signals;

a shift register configured to sequentially enable a given latch at a time of the plurality of clock gating latches to provide a respective phase delay offset clock signal to as the spread clock output signal; and

a state machine configured to instruct the shift register to count up to sequentially provide increasing phase delay offset clock signals, count down to sequentially provide decreasing phase delay offset clock signals and hold a current phase delay offset clock signal at the spread clock output signal.

8. The system of claim 7, wherein the clock spread system employs triangular modulation by sequentially selecting between the plurality of phase delay offset clock signals in increasing increments from a zero phase delay offset to a maximum phase delay offset and sequentially selecting between the plurality of phase delay offset clock signals in decreasing increments from the maximum phase delay offset to the zero phase delay offset.

9. The system of claim 8, further comprising:

a random number generator configured to generate a random number every clock cycle;

a delay counter configured to repeat counting from a first value to a second value and instruct the random number generator to hold its current random number value after reaching the second value; and

wherein the state machine continuously instructs the shifter register to repeat the triangular modulation and is configured to hold the spread clock output signal at the zero phase delay offset and the maximum phase delay offset for a pseudo-random period of time in the transmit mode while the held current random number value is in a first state and to continue counting up or down when the held current random number value is in a second state, and the state machine holds the spread clock output signal at the zero phase delay offset and the maximum phase delay offset for a predetermined period of time in the receive mode.

10. The system of claim 7, wherein the state machine and the shift register are clocked by the spread clock output signal, which causes the spread clock output signal to have a frequency that is lower than a reference frequency of the clock reference signal during the increasing increments and a frequency that is higher than the reference frequency during the decreasing increments.

11. The system of claim 10, wherein the clock spreading system is glitch free since a previous and a next phase delay offset clock signal are both in a high state when switching between phase delay offset clock signals.

12. An integrated circuit comprising the system of claim 1, and further comprising:

an antenna coupled to the integrated circuit;

a controller coupled to the integrated circuit;

a memory system coupled to the controller;

an Input/Output (I/O) interface coupled to the controller; and

a power supply for powering the integrated circuit.

13. A clock spreading system comprising:

a delay line logic device that receives a clock reference signal and provides a plurality of phase delay offset clock signals sequentially spaced apart in predetermined phase delay offset increments;

a plurality of clock gating latches with a given latch receiving a respective phase delay offset clock signal for each of the plurality of phase delay offset clock signals;

a shift register configured to sequentially enable a given latch at a time of the plurality of clock gating latches to provide a respective phase delay offset clock signal as a spread clock output signal; and

a state machine configured to instruct the shift register to count up to sequentially provide increasing phase delay offset clock signals, count down to sequentially provide decreasing phase delay offset clock signals and hold a current phase delay offset clock signal at the spread clock output signal;

wherein the state machine and the shift register are clocked by the spread clock output signal, which causes the spread clock output signal to have a frequency that is lower than a reference frequency of the clock reference signal during increasing phase delay offset clock signals and a frequency that is higher than the reference frequency during decreasing phase delay offset clock signals.

14. The system of claim 13, wherein the clock spread system employs triangular modulation by sequentially selecting between the plurality of phase delay offset clock signals in increasing increments from a zero phase delay offset to a maximum phase delay offset and sequentially selecting between the plurality of phase delay offset clock signals in decreasing increments from the maximum phase delay offset to the zero phase delay offset.

15. The system of claim 14, further comprising:

a random number generator configured to generate a random number every clock cycle;

a delay counter configured to repeat counting from a first value to a second value and instruct the random number generator to hold its current random number value after reaching the second value; and

wherein the state machine continuously instructs the shifter register to repeat the increasing up and decreasing down and is configured to hold the spread clock output signal at the zero phase delay offset and the maximum phase delay offset for a pseudo-random period of time in the transmit mode while the held current random number value is in a first state and to continue counting up or down when the held current random number value is in a second state, and the state machine holds the spread clock output signal at the zero phase delay offset and the maximum phase delay offset for a predetermined period of time in the receive mode.

16. The system of claim 13, wherein the clock spreading system is glitch free since a previous and a next phase delay offset clock signal are both in a high state when switching between phase delay offset clock signals.

17. A method of spreading a clock signal, the method comprising:

providing a plurality of phase delay offset clock signals sequentially spaced apart in predetermined phase delay offset increments from a reference frequency;

sequentially providing one at a time increasing respective phase delay offset clock signals as a spread clock output signal from a zero phase delay offset to a maximum phase delay offset;

holding the spread clock output signal at the maximum phase delay offset for a pseudo-random period of time in a transmit mode;

holding the spread clock output signal at the maximum phase delay offset for a predetermined period of time in a receive mode; and

sequentially providing one at a time decreasing respective phase delay offset clock signals as the spread clock output signal from the maximum phase delay offset to the zero phase delay offset.

18. The method of claim 17, further comprising continuously repeating the method of claim 17 and further comprising holding the spread clock output signal at the zero phase delay offset for a pseudo-random period of time in the transmit mode and holding the spread clock output signal at the zero phase delay offset for a predetermined period of time in the receive mode.

19. The method of claim 17, wherein the spread clock output signal has a frequency that is lower than the reference frequency during the increasing increments and a frequency that is higher than the reference frequency during the decreasing increments.

20. The method of claim 17, further comprising transmitting data in the transmit mode and receiving data in the receive mode.