Shift Register

• US 20100245300A1
• Filed: 03/19/2010
• Published: 09/30/2010
• Est. Priority Date: 03/25/2009
• Status: Active Grant

• Current Assignee: Wintek Corporation
• Original Assignee: Wintek Corporation
• Inventors: Su, Kuo-Chang, Han, Hsi-Rong, Wang, Wen-Chun, Chan, Chien-Ting
• Granted Patent: US 8,970,467 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift register including a plurality of multi-stage shift register circuits is provided. The m^th stage shift register circuit includes a node, a shift register unit and a control circuit. A first control signal, enabled in an m^th period, is defined on the node. The shift register unit is controlled by an (m−1)^th stage output signal provided by an (m−1)^th stage shift register circuit and a clock signal for providing the enabled m^th stage output signal in the m^th period, and controlled by an (m+1)^th stage second control signal provided by an (m+1)^th stage shift register circuit for providing a disenabled m^th stage output signal in the (m+1)^th period. The control circuit, controlled by the clock signal, provides and outputs an m^th stage second control signal to the (m−1)^th stage shift register circuit according to the m^th stage first control signal, wherein m is a natural number greater than 1.

Claims

1. A shift register comprises a plurality of multi-stage shift register circuits respectively used for outputting a plurality of shift output signals, wherein an m^th stage shift register circuit of the multi-stage shift register circuits comprises:

an m^th stage first node, wherein an m^th stage first control signal enabled in an m^th period is defined on the m^th stage first node;

an m^th stage shift register unit controlled by an (m−

1)^th stage output signal, which is enabled in an (m−

1)^th period and provided by an (m−

1)^th stage shift register circuit, and a first clock signal for providing an enabled m^th stage output signal in the m^th period, wherein the m^th stage shift register unit further is controlled by an (m+1)^th stage second control signal provided by an (m+1)^th stage shift register circuit for providing the disenabled m^th stage output signal in an (m+1)^th period; and

an m^th stage control circuit controlled by the first clock signal for providing and outputting an m^th stage second control signal to the (m−

1)^th stage shift register circuit according to the m^th stage first control signal;

wherein m is a natural number greater than 1.

2. The shift register according to claim 1, wherein the m^th stage control circuit comprises:

a second node, wherein the m^th stage second control signal is defined on the second node;

a first transistor, wherein a first input end is coupled to the m^th stage first node, a second input end is coupled to the second node, and the control end receives the first clock signal; and

a second transistor, wherein the first input end is coupled to the second node, the second input end receives a reference voltage signal, and the control end receives a second clock signal.

3. The shift register according to claim 2, wherein the m^th stage control circuit further comprises:

a third transistor, wherein the first input end receives the (m−

1)^th stage output signal, the second input end is coupled to the m^th stage first node, and the control end receives the second clock signal.

4. The shift register according to claim 3, wherein the first clock signal and the second clock signal are inversed.

5. The shift register according to claim 1, wherein the (m+1)^th stage shift register circuit comprises:

an (m+1)^th stage first node, wherein an (m+1)^th stage first control signal enabled in the (m+1)^th period is defined on the (m+1)^th stage first node;

an (m+1)^th stage shift register unit controlled by the m^th stage output signal provided by the m^th stage shift register circuit and a second clock signal for providing an enabled (m+1)^th stage output signal in the (m+1)^th period, wherein the (m+1)^th stage shift register unit further is controlled by an (m+2)^th stage second control signal provided by an (m+2)^th stage shift register circuit for providing the disenabled (m+1)^th stage output signal in an (m+2)^th period; and

an (m+1)^th stage control circuit controlled by the second clock signal for providing and outputting the (m+1)^th stage second control signal to the m^th stage shift register circuit according to the (m+1)^th stage first control signal.

6. The shift register according to claim 5, wherein the first clock signal and the second clock signal are inversed.

7. The shift register according to claim 1, wherein the (m−

1)^th stage shift register circuit comprises;

an (m−

1)^th stage first node, wherein an (m−

1)^th stage first control signal enabled in the (m−

1)^th period is defined on the (m−

1)^th stage first node;

an (m−

1)^th stage shift register unit controlled by the (m−

2)^th stage output signal provided by the (m−

2)^th stage shift register circuit and a second clock signal for providing an enabled (m−

1)^th stage output signal in the (m−

1)^th period, wherein the (m−

1)^th stage shift register unit further is controlled by the m^th stage second control signal provided by the m^th stage shift register circuit for providing the disenabled (m−

1)^th stage output signal in the m^th period; and

an (m−

1)^th stage control circuit controlled by the second clock signal for providing and outputting the (m−

1)^th stage second control signal to the (m−

2)^th stage shift register circuit according to the (m−

1)^th stage first control signal.

8. The shift register according to claim 7, wherein the first clock signal and the second clock signal are inversed.

9. The shift register according to claim 1, wherein the m^th stage shift register unit comprises:

a first level control unit used for providing a first clock signal as the m^th stage output signal;

a first driving unit, wherein the first driving unit and an input end of the first level control unit are coupled to the m^th stage first node, and the first driving unit is used for turning on the first level control unit in the m^th and the (m+1)^th period and turning off the first level control unit in the (m+2)^th period in response to the front edge of the (m−

1)^th stage output signal according to the (m+1)^th stage second control signal;

a second level control unit used for providing a reference voltage signal as the m^th stage output signal; and

a second driving unit used for disenabling the second level control unit in the (m−

1)^th period and the m^th period in response to the front edge of the m^th stage first control signal and turning on the second level control unit in response to the rear edge of the m^th stage first control signal.

10. The shift register according to claim 1, wherein the N shift output signals provided by the N shift register circuits are used as odd-order gate signal for driving a display panel, and the (m−

1)^th stage, the m^th stage and the (m+1)^th stage output signal respectively drive the j^th row, the (j+1)^th row and the (j+2)^th row of pixels of the display panel, and j is an odd number.

11. The shift register according to claim 1, wherein the N shift output signals provided by the N shift register circuits are used as even-order gate signal for driving a display panel, and the (m−

1)^th stage, the m^th stage and the (m+1)^th stage output signal respectively drive the i^th row, the (i+1)^th row and the (i+2)^th row of pixels of the display panel, and i is an even number.

12. The shift register according to claim 1, wherein the N shift output signals provided by the N shift register circuits are used for driving the gate signals of a display panel, the (m−

1)^th stage, the m^th stage and the (m+1)^th stage output signal respectively drive the k^th row, the (k+1)^th row and the (k+2)^th row of pixels of the display panel, and k is an odd number.

13. A gate driver used for driving a display panel, wherein the gate driver comprises:

a shift register comprising a plurality of multi-stage shift register circuits respectively used for outputting a plurality of shift output signals, wherein an m^th stage shift register circuit of the multi-stage shift register circuits comprises;

an m^th stage first node, wherein an m^th stage first control signal enabled in an m^th period is defined on the m^th stage first node;

an m^th stage shift register unit controlled by an (m−

1)^th stage output signal, which is provided by an (m−

1)^th stage shift register circuit and enabled in an (m−

1)^th period, and a first clock signal for providing an enabled m^th stage output signal in the m^th period, wherein the m^th stage shift register unit further is controlled by an (m+1)^th stage second control signal provided by an (m+1)^th stage shift register circuit for providing the disenabled m^th stage output signal in an (m+1)^th period; and

an m^th stage control circuit controlled by the first clock signal for providing and outputting an m^th stage second control signal to the (m−

1)^th stage shift register circuit according to the m^th stage first control signal;

wherein m is a natural number greater than 1.

14. The gate driver according to claim 13, wherein the m^th stage control circuit comprises:

a second node, wherein the m^th stage second control signal is defined on the second node;

a first transistor, wherein a first input end is coupled to the m^th stage first node, a second input end is coupled to the second node, and the control end receives the first clock signal; and

a second transistor, wherein the first input end is coupled to the second node, the second input end receives a reference voltage signal, and the control end receives a second clock signal.

15. The gate driver according to claim 14, wherein the m^th stage control circuit further comprises:

a third transistor, wherein the first input end receives the (m−

1)^th stage output signal, the second input end is coupled to the m^th stage first node, and the control end receives the second clock signal.

16. The gate driver according to claim 15, wherein the first clock signal and the second clock signal are inversed.

17. The gate driver according to claim 13, wherein the display panel uses dual-gate layout.

18. The gate driver according to claim 13, wherein the display panel uses triple-gate layout.

19. The gate driver according to claim 13, wherein the display panel uses delta layout.