STORAGE CAPACITOR LINE DRIVE CIRCUIT AND DISPLAY DEVICE

• US 20100245328A1
• Filed: 08/21/2008
• Published: 09/30/2010
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Sasaki, Yasushi, Furuta, Shige, Murakami, Yuhichiroh, Yokoyama, Makoto
• Granted Patent: US 8,587,572 B2
• Time in Patent Office: Days
• US Class Current: 345/211
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0219 Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET

Abstract

In a storage capacitor line drive circuit driving a storage capacitor line of an active-matrix display device and driven by outputs of a scanning signal line drive circuit, at least one (VSS) of a high-potential supply voltage (VDD) and a low-potential supply voltage (VSS) differs from a supply voltage (GVSS) of a corresponding logical level of the scanning signal line drive circuit, the high-potential supply voltage and the low-potential supply voltage being used for generating a signal voltage of a preceding stage to an output stage. This makes it possible to achieve a storage capacitor line drive circuit capable of avoiding malfunctioning even in a case where the storage capacitor line drive circuit receives noise from a scanning signal line, and a display device including the storage capacitor line drive circuit.

Claims

1. A storage capacitor line drive circuit driving a storage capacitor line of an active-matrix display device and driven by outputs of a scanning signal line drive circuit, the storage capacitor line drive circuit comprising as transistors a plurality of transistors having an identical conductivity type, wherein:

at least one of a high-potential supply voltage and a low-potential supply voltage differs from a supply voltage of a corresponding logical level of the scanning signal line drive circuit,

the high-potential supply voltage and the low-potential supply voltage being used for generating a signal voltage of a preceding stage to an output stage.

2. The storage capacitor line drive circuit according to claim 1, wherein all the transistors are n-channel-polarity transistors.

3. The storage capacitor line drive circuit according to claim 2, wherein the low-potential supply voltage for generating the signal voltage of the storage capacitor line drive circuit is higher than a low-potential supply voltage for generating an output of the scanning signal line drive circuit.

4. The storage capacitor line drive circuit according to claim 1, wherein all the transistors are p-channel-polarity transistors.

5. The storage capacitor line drive circuit according to claim 4, wherein the high-potential supply voltage for generating the signal voltage of the storage capacitor line drive circuit is lower than a high-potential supply voltage for generating an output of the scanning signal line drive circuit.

6. The storage capacitor line drive circuit according to claim 1, comprising stages corresponding to each of the outputs of the scanning signal line drive circuit,

each of the stages including a first switch, a first memory circuit, a first transfer switch, a first analog switch, a second switch, a second memory circuit, a second transfer switch, and a second analog switch,

the first analog switch and the second analog switch being included in the output stage,

the first switch being provided between the first memory circuit and an input terminal for a first polarity determination signal instructing a polarity of a storage capacitor voltage, the first switch turning on and off according to one of the outputs as a control signal, the one of the outputs being from the scanning signal line drive circuit corresponding to one of the stage,

the first memory circuit storing the first polarity determination signal taken in through the first switch and outputting as a first stored signal the first polarity determination signal,

the first transfer switch transferring as a first transferred signal the first stored signal outputted from the first memory circuit, in accordance with a timing of a clock signal inputted;

the first analog switch being provided between an output terminal to the storage capacitor line of the one of the stages and a high-potential supply of the storage capacitor voltage, the first analog switch turning on and off according to the first transferred signal as a control signal, the first transferred signal being transferred from the first transfer switch,

the second switch being provided between the second memory circuit and an input terminal for a second polarity determination signal having a polarity opposite to that of the first polarity determination signal instructing the polarity of the storage capacitor voltage, the second switch turning on and off according to the one of the outputs as a control signal, the one of the outputs being from the scanning signal line drive circuit corresponding to the one of the stage,

the second memory circuit storing the second polarity determination signal taken in through the second switch and outputting as a second stored signal the second polarity determination signal,

the second transfer switch transferring as a second transferred signal the second stored signal outputted from the second memory circuit, in accordance with the timing of the clock signal inputted,

the second analog switch being provided between the output terminal of the one of the stages and a low-potential supply of the storage capacitor voltage, the second analog switch turning on and off according to the second transferred signal as a control signal, the second transferred signal being transferred from the second transfer switch,

each of the first polarity reversal signal, the first stored signal, the first transferred signal, the second polarity reversal signal, the second stored signal and the second transferred signal having a voltage of the signal voltage.

7. The storage capacitor line drive circuit according to claim 6, wherein the first switch and the second switch are transistors.

8. The storage capacitor line drive circuit according to claim 6, wherein:

the first memory circuit is a capacitor connected between (i) an output terminal of the first switch and an input terminal of the first transfer switch on one side and (ii) a low-potential supply of the first stored signal on the other side; and

the second memory circuit is a capacitor connected between (i) an output terminal of the second switch and an input terminal of the second transfer switch on one side and (ii) a low-potential supply of the second stored signal on the other side.

9. The storage capacitor line drive circuit according to claim 6, wherein the first transfer switch and the second transfer switch are transistors turning on and off according to the clock signal as a control signal.

10. A display device comprising the storage capacitor line drive circuit according to claim 1.

11. The display device according to claim 10, wherein the storage capacitor line drive circuit and the scanning signal line drive circuit are formed so as to sandwich the scanning signal line and be separated from each other.

12. The display device in accordance with claim 10, wherein both the storage capacitor line drive circuit and the scanning signal drive circuit are formed at one end of the scanning signal line.