×

INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY

  • US 20100246152A1
  • Filed: 03/11/2010
  • Published: 09/30/2010
  • Est. Priority Date: 03/30/2009
  • Status: Active Grant
First Claim
Patent Images

1. A module comprising:

  • a substrate;

    a processor unit on said substrate, wherein said processor unit comprises a first cache memory chip over said substrate and a processor chip over said first cache memory chip, wherein said first cache memory chip is connected to said processor chip through a plurality of microbumps between said first cache memory chip and said processor chip, wherein a pitch between a neighboring two of said plurality of microbumps is smaller than 60 micrometers;

    a mass storage on said substrate, wherein said mass storage comprises a first memory chip over said substrate and a second memory chip over said first memory chip, wherein said first memory chip is connected to said second memory chip through at least one first wirebonded wire;

    a main memory on said substrate, wherein said main memory comprises a first dynamic-random-access-memory chip over said substrate and a second dynamic-random-access-memory chip over said first dynamic-random-access-memory chip; and

    a connector connected to said substrate.

View all claims
  • 3 Assignments
Timeline View
Assignment View
    ×
    ×