INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY
First Claim
Patent Images
1. A module comprising:
- a substrate;
a processor unit on said substrate, wherein said processor unit comprises a first cache memory chip over said substrate and a processor chip over said first cache memory chip, wherein said first cache memory chip is connected to said processor chip through a plurality of microbumps between said first cache memory chip and said processor chip, wherein a pitch between a neighboring two of said plurality of microbumps is smaller than 60 micrometers;
a mass storage on said substrate, wherein said mass storage comprises a first memory chip over said substrate and a second memory chip over said first memory chip, wherein said first memory chip is connected to said second memory chip through at least one first wirebonded wire;
a main memory on said substrate, wherein said main memory comprises a first dynamic-random-access-memory chip over said substrate and a second dynamic-random-access-memory chip over said first dynamic-random-access-memory chip; and
a connector connected to said substrate.
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Accused Products
Abstract
Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.
371 Citations
20 Claims
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1. A module comprising:
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a substrate; a processor unit on said substrate, wherein said processor unit comprises a first cache memory chip over said substrate and a processor chip over said first cache memory chip, wherein said first cache memory chip is connected to said processor chip through a plurality of microbumps between said first cache memory chip and said processor chip, wherein a pitch between a neighboring two of said plurality of microbumps is smaller than 60 micrometers; a mass storage on said substrate, wherein said mass storage comprises a first memory chip over said substrate and a second memory chip over said first memory chip, wherein said first memory chip is connected to said second memory chip through at least one first wirebonded wire; a main memory on said substrate, wherein said main memory comprises a first dynamic-random-access-memory chip over said substrate and a second dynamic-random-access-memory chip over said first dynamic-random-access-memory chip; and a connector connected to said substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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2. The module of claim 1, wherein the module is implemented in a computer, a mobile phone, a mobile compuphone, a camera, an electronic book, a digital picture frame, an automobile electronic product, a 3D video display, a 3D television, a 3D video game player, a projector, or a server used for cloud computing.
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3. The module of claim 1, wherein said processor chip comprises a central-processing-unit (CPU) circuit block designed by x86 architecture or by non x86 architectures, a graphics-processing-unit (GPU) circuit block, a baseband circuit block, a digital-signal-processing (DSP) circuit block, or a wireless local area network (WLAN) circuit block.
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4. The module of claim 1, wherein said processor chip comprises a central-processing-unit (CPU) chip designed by x86 architecture or by non x86 architectures.
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5. The module of claim 1, wherein said processor chip comprises a system-on chip (SOC) comprising a baseband circuit block, a wireless local area network (WLAN) circuit block and a central-processing-unit (CPU) circuit block designed by x86 architecture or by non x86 architectures, but not comprising any graphics-processing-unit (GPU) circuit block.
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6. The module of claim 1, wherein said first cache memory chip comprises a dynamic-random-access-memory (DRAM) chip, a synchronous-dynamic-random-access-memory (SDRAM) chip, or a static-random-access-memory (SRAM) chip.
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7. The module of claim 1, wherein said first cache memory chip has a memory size between 10 megabytes and 32 gigabytes.
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8. The module of claim 1, wherein said first cache memory chip is connected to said substrate through at least one second wirebonded wire.
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9. The module of claim 1, wherein said first cache memory chip comprises a silicon substrate, a plurality of through-silicon vias in said silicon substrate, a bottom scheme at a backside of said silicon substrate and in said plurality of through-silicon vias, a first dielectric layer over a top side of said silicon substrate, a first metal layer over said first dielectric layer, a second dielectric layer over said first metal layer, a second metal layer over said second dielectric layer, and a passivation layer over said top side of said silicon substrate, over said first and second dielectric layers and over said first and second metal layers, wherein each of a plurality of openings in said passivation layer is over a respective one of a plurality of contact points of said second metal layer, and said plurality of contact points is at bottoms of said plurality of openings, wherein said plurality of microbumps is connected to said plurality of contact points through said plurality of openings, wherein said bottom scheme comprises a metal bump between said silicon substrate and said substrate, wherein said first cache memory chip is connected to said substrate through said metal bump.
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10. The module of claim 1, wherein said first memory chip comprises a flash memory chip or a dynamic-random-access-memory (DRAM) chip.
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11. The module of claim 1, wherein said processor unit further comprises a second cache memory chip over said processor chip, wherein said second cache memory chip is connected to said processor chip.
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12. The module of claim 1, wherein said second memory chip has a right portion overhanging said first memory chip, and said first memory chip has a left portion not vertically under said second memory chip, wherein said second memory chip has a left sidewall recessed from that of said first memory chip.
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13. The module of claim 1 further comprising a radio frequency (RF) module on said substrate.
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14. The module of claim 1, wherein said first dynamic-random-access-memory chip comprises a first silicon substrate, a first dielectric layer over said first silicon substrate, a first metal layer over said first dielectric layer, a second dielectric layer over said first metal layer, a second metal layer over said second dielectric layer, and a first passivation layer over said first silicon substrate, over said first and second dielectric layers and over said first and second metal layers, wherein each of a plurality of openings in said first passivation layer is over a respective one of a plurality of contact points of said second metal layer, and said plurality of contact points is at bottoms of said plurality of openings, wherein said second dynamic-random-access-memory chip comprises a second silicon substrate, a plurality of through-silicon vias in said second silicon substrate, a bottom scheme at a backside of said second silicon substrate and in said plurality of through-silicon vias, a third dielectric layer over a top side of said second silicon substrate, a third metal layer over said third dielectric layer, a fourth dielectric layer over said third metal layer, a fourth metal layer over said fourth dielectric layer, and a second passivation layer over said top side of said second silicon substrate, over said third and fourth dielectric layers and over said third and fourth metal layers, wherein said bottom scheme comprises a metal bump between said second silicon substrate and said first dynamic-random-access-memory chip, wherein said metal bump is connected to one of said plurality of contact points through one of said plurality of openings, wherein said second dynamic-random-access-memory chip is connected to said first dynamic-random-access-memory chip through said metal bump.
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15. The module of claim 1, wherein said connector is used for connecting to a charger, a game player, a display, or a television.
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16. The module of claim 1, wherein said connector comprises a universal serial bus (USB), a high-definition multimedia interface (HDMI), a DisplayPort, an IEEE 1394, or an optical connector.
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17. The module of claim 1, wherein said first cache memory chip comprises a first metal pad, a second metal pad, a testing interface circuit having a first node connected to said first metal pad, a first inter-chip buffer connected to said first metal pad and to said first node of said testing interface circuit, an off-chip buffer having a first node connected to a second node of said testing interface circuit and a second node connected to said second metal pad, and an off-chip electro static discharge (ESD) circuit connected to said second node of said off-chip buffer and to said second metal pad, wherein one of said plurality of microbumps is on said first metal pad, wherein said one of said plurality of microbumps is connected to said first inter-chip buffer and to said first node of said testing interface circuit through said first metal pad, wherein said second metal pad is not connected upwards to said processor chip through any microbump between said first cache memory chip and said processor chip.
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18. The module of claim 17, wherein said off-chip buffer comprises a first NMOS transistor, and said first inter-chip buffer comprises a second NMOS transistor, wherein a ratio of a physical channel width to a physical channel length of said first NMOS transistor is greater than a ratio of a physical channel width to a physical channel length of said second NMOS transistor by more than 3 times.
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19. The module of claim 17, wherein said processor chip comprises a third metal pad and a second inter-chip buffer connected to said third metal pad, wherein said one of said plurality of microbumps is between said first and third metal pads, wherein said one of said plurality of microbumps is connected to said second inter-chip buffer through said third metal pad, wherein said first inter-chip buffer is connected to said second inter-chip buffer through, in sequence, said first metal pad, said one of said plurality of microbumps, and said third metal pad.
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20. The module of claim 19, wherein there is no electro static discharge (ESD) circuit connected to a path between said first inter-chip buffer and said second inter-chip buffer.
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2. The module of claim 1, wherein the module is implemented in a computer, a mobile phone, a mobile compuphone, a camera, an electronic book, a digital picture frame, an automobile electronic product, a 3D video display, a 3D television, a 3D video game player, a projector, or a server used for cloud computing.
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Specification
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Current AssigneeQualcomm, Inc.
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Original AssigneeMegica Corporation (Chipbond Technology Corporation)
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InventorsLiu, Te-Sheng, Yang, Ping-Jung, Lin, Mou-Shiung, Lee, Jin-Yuan, Lo, Hsin-Jung
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current361/783
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CPC Class CodesG06F 1/16 Constructional details or a...G11C 5/147 Voltage reference generator...H01L 21/304 Mechanical treatment, e.g. ...H01L 21/56 Encapsulations, e.g. encaps...H01L 21/563 Encapsulation of active fac...H01L 21/76898 formed through a semiconduc...H01L 21/78 with subsequent division of...H01L 2223/6611 Wire connectionsH01L 2223/6666 for decoupling, e.g. bypass...H01L 2224/02166 Collar structuresH01L 2224/0231 Manufacturing methods of th...H01L 2224/02311 Additive methodsH01L 2224/02313 Subtractive methodsH01L 2224/02321 ReworkingH01L 2224/0233 Structure of the redistribu...H01L 2224/02331 Multilayer structureH01L 2224/0235 Shape of the redistribution...H01L 2224/0237 Disposition of the redistri...H01L 2224/02371 connecting the bonding area...H01L 2224/02375 Top viewH01L 2224/02381 : Side viewH01L 2224/0239 : Material of the redistribut...H01L 2224/024 : Material of the insulating ...H01L 2224/03 : Manufacturing methodsH01L 2224/0345 : Physical vapour deposition ...H01L 2224/03462 : ElectroplatingH01L 2224/03464 : Electroless platingH01L 2224/0361 : Physical or chemical etchingH01L 2224/03612 : by physical means onlyH01L 2224/03614 : by chemical means onlyH01L 2224/03912 : the bump being used as a ma...H01L 2224/0392 : specifically adapted to inc...H01L 2224/0401 : Bonding areas specifically ...H01L 2224/04042 : Bonding areas specifically ...H01L 2224/05024 : the internal layer being di...H01L 2224/05027 : the internal layer extendin...H01L 2224/05155 : Nickel [Ni] as principal co...H01L 2224/05166 : Titanium [Ti] as principal ...H01L 2224/05171 : Chromium [Cr] as principal ...H01L 2224/05176 : Ruthenium [Ru] as principal...H01L 2224/05181 : Tantalum [Ta] as principal ...H01L 2224/05187 : Ceramics, e.g. crystalline ...H01L 2224/05541 : StructureH01L 2224/05548 : Bonding area integrally for...H01L 2224/05554 : being squareH01L 2224/0556 : DispositionH01L 2224/05567 : the external layer being at...H01L 2224/05572 : the external layer extendin...H01L 2224/056 : with a principal constituen...H01L 2224/05624 : Aluminium [Al] as principal...H01L 2224/05639 : Silver [Ag] as principal co...H01L 2224/05644 : Gold [Au] as principal cons...H01L 2224/05647 : Copper [Cu] as principal co...H01L 2224/05655 : Nickel [Ni] as principal co...H01L 2224/05664 : Palladium [Pd] as principal...H01L 2224/05669 : Platinum [Pt] as principal ...H01L 2224/05673 : Rhodium [Rh] as principal c...H01L 2224/05676 : Ruthenium [Ru] as principal...H01L 2224/11 : Manufacturing methodsH01L 2224/11009 : for protecting parts during...H01L 2224/1132 : Screen printing, i.e. using...H01L 2224/11334 : using preformed bumpsH01L 2224/11462 : ElectroplatingH01L 2224/11464 : Electroless platingH01L 2224/1147 : using a lift-off maskH01L 2224/11849 : ReflowingH01L 2224/119 : Methods of manufacturing bu...H01L 2224/1191 : Forming a passivation layer...H01L 2224/13 : of an individual bump conne...H01L 2224/13006 : Bump connector larger than ...H01L 2224/1302 : DispositionH01L 2224/13022 : the bump connector being at...H01L 2224/13024 : the bump connector being di...H01L 2224/13082 : Two-layer arrangementsH01L 2224/13083 : Three-layer arrangementsH01L 2224/13084 : Four-layer arrangementsH01L 2224/13099 : MaterialH01L 2224/131 : with a principal constituen...H01L 2224/13109 : Indium [In] as principal co...H01L 2224/13111 : Tin [Sn] as principal const...H01L 2224/13113 : Bismuth [Bi] as principal c...H01L 2224/13124 : Aluminium [Al] as principal...H01L 2224/13139 : Silver [Ag] as principal co...H01L 2224/13144 : Gold [Au] as principal cons...H01L 2224/13147 : Copper [Cu] as principal co...H01L 2224/13155 : Nickel [Ni] as principal co...H01L 2224/13164 : Palladium [Pd] as principal...H01L 2224/13169 : Platinum [Pt] as principal ...H01L 2224/13294 : with a principal constituen...H01L 2224/133 : with a principal constituen...H01L 2224/13311 : Tin [Sn] as principal const...H01L 2224/13609 : Indium [In] as principal co...H01L 2224/1403 : Bump connectors having diff...H01L 2224/1411 : the bump connectors being b...H01L 2224/14181 : On opposite sides of the bodyH01L 2224/16145 : the bodies being stackedH01L 2224/16225 : the item being non-metallic...H01L 2224/16227 : the bump connector connecti...H01L 2224/16245 : the item being metallicH01L 2224/16265 : the item being a discrete p...H01L 2224/17181 : On opposite sides of the bodyH01L 2224/2919 : with a principal constituen...H01L 2224/2929 : with a principal constituen...H01L 2224/29294 : with a principal constituen...H01L 2224/293 : with a principal constituen...H01L 2224/29339 : Silver [Ag] as principal co...H01L 2224/32105 : the layer connector connect...H01L 2224/32145 : the bodies being stackedH01L 2224/32225 : the item being non-metallic...H01L 2224/32245 : the item being metallicH01L 2224/33181 : On opposite sides of the bodyH01L 2224/45124 : Aluminium (Al) as principal...H01L 2224/45144 : Gold (Au) as principal cons...H01L 2224/45147 : Copper (Cu) as principal co...H01L 2224/48091 : ArchedH01L 2224/48111 : the wire connector extendin...H01L 2224/48145 : the bodies being stackedH01L 2224/48227 : connecting the wire to a bo...H01L 2224/48247 : connecting the wire to a bo...H01L 2224/48465 : the other connecting portio...H01L 2224/48624 : Aluminium (Al) as principal...H01L 2224/48644 : Gold (Au) as principal cons...H01L 2224/48647 : Copper (Cu) as principal co...H01L 2224/48664 : Palladium (Pd) as principal...H01L 2224/48669 : Platinum (Pt) as principal ...H01L 2224/48744 : Gold (Au) as principal cons...H01L 2224/48764 : Palladium (Pd) as principal...H01L 2224/48769 : Platinum (Pt) as principal ...H01L 2224/48824 : Aluminium (Al) as principal...H01L 2224/48844 : Gold (Au) as principal cons...H01L 2224/48847 : Copper (Cu) as principal co...H01L 2224/48864 : Palladium (Pd) as principal...H01L 2224/48869 : Platinum (Pt) as principal ...H01L 2224/4911 : the connectors being bonded...H01L 2224/49175 : Parallel arrangementsH01L 2224/4918 : being disposed on at least ...H01L 2224/73203 : Bump and layer connectorsH01L 2224/73204 : the bump connector being em...H01L 2224/73207 : Bump and wire connectorsH01L 2224/73215 : Layer and wire connectorsH01L 2224/73253 : Bump and layer connectorsH01L 2224/73257 : Bump and wire connectorsH01L 2224/73265 : Layer and wire connectorsH01L 2224/81 : using a bump connectorH01L 2224/81191 : wherein the bump connectors...H01L 2224/81411 : Tin [Sn] as principal const...H01L 2224/81444 : Gold [Au] as principal cons...H01L 2224/81801 : Soldering or alloyingH01L 2224/81815 : Reflow solderingH01L 2224/8185 : using a polymer adhesive, e...H01L 2224/81895 : between electrically conduc...H01L 2224/81903 : by means of a layer connectorH01L 2224/83 : using a layer connectorH01L 2224/83101 : as prepeg comprising a laye...H01L 2224/83104 : by applying pressure, e.g. ...H01L 2224/83851 : being an anisotropic conduc...H01L 2224/85 : using a wire connectorH01L 2224/92 : Specific sequence of method...H01L 2224/9202 : Forming additional connecto...H01L 2224/92125 : the second connecting proce...H01L 2224/92127 : the second connecting proce...H01L 2224/92147 : the second connecting proce...H01L 2224/92225 : the second connecting proce...H01L 2224/92247 : the second connecting proce...H01L 2224/94 : at wafer-level, i.e. with c...H01L 2224/97 : the devices being connected...H01L 2225/06506 : Wire or wire-like electrica...H01L 2225/0651 : Wire or wire-like electrica...H01L 2225/06513 : Bump or bump-like direct el...H01L 2225/06517 : Bump or bump-like direct el...H01L 2225/06541 : Conductive via connections ...H01L 2225/06562 : at least one device in the ...H01L 2225/06589 : Thermal management, e.g. co...H01L 2225/1023 : the support being an insula...H01L 2225/1029 : the support being a lead frameH01L 2225/1058 : Bump or bump-like electrica...H01L 2225/107 : Indirect electrical connect...H01L 23/3128 : the substrate having spheri...H01L 23/3171 : the coating being directly ...H01L 23/3192 : Multilayer coatingH01L 23/481 : Internal lead connections, ...H01L 23/5223 : Capacitor integral with wir...H01L 23/5227 : Inductive arrangements or e...H01L 23/60 : Protection against electros...H01L 23/66 : High-frequency adaptationsH01L 24/02 : Bonding areas on insulating...H01L 24/03 : Manufacturing methodsH01L 24/05 : of an individual bonding areaH01L 24/06 : of a plurality of bonding a...H01L 24/11 : Manufacturing methods for b...H01L 24/13 : of an individual bump conne...H01L 24/14 : of a plurality of bump conn...H01L 24/16 : of an individual bump conne...H01L 24/17 : of a plurality of bump conn...H01L 24/29 : of an individual layer conn...H01L 24/32 : of an individual layer conn...H01L 24/33 : of a plurality of layer con...H01L 24/45 : of an individual wire conne...H01L 24/48 : of an individual wire conne...H01L 24/49 : of a plurality of wire conn...H01L 24/50 : Tape automated bonding [TAB...H01L 24/73 : Means for bonding being of ...H01L 24/78 : Apparatus for connecting wi...H01L 24/81 : using a bump connectorH01L 24/83 : using a layer connectorH01L 24/85 : using a wire connector wire...H01L 24/86 : using tape automated bondin...H01L 24/92 : Specific sequence of method...H01L 24/94 : at wafer-level, i.e. with c...H01L 24/97 : the devices being connected...H01L 25/0657 : Stacked arrangements of dev...H01L 25/16 : the devices being of types ...H01L 25/18 : the devices being of types ...H01L 25/50 : Multistep manufacturing pro...H01L 2924/00 : Indexing scheme for arrange...H01L 2924/00012 : Relevant to the scope of th...H01L 2924/00014 : the subject-matter covered ...H01L 2924/01005 : Boron [B]H01L 2924/01006 : Carbon [C]H01L 2924/01007 : Nitrogen [N]H01L 2924/01011 : Sodium [Na]H01L 2924/01013 : Aluminum [Al]H01L 2924/01014 : Silicon [Si]H01L 2924/01015 : Phosphorus [P]H01L 2924/01018 : Argon [Ar]H01L 2924/01019 : Potassium [K]H01L 2924/0102 : Calcium [Ca]H01L 2924/01022 : Titanium [Ti]H01L 2924/01023 : Vanadium [V]H01L 2924/01024 : Chromium [Cr]H01L 2924/01027 : Cobalt [Co]H01L 2924/01028 : Nickel [Ni]H01L 2924/01029 : Copper [Cu]H01L 2924/01031 : Gallium [Ga]H01L 2924/01032 : Germanium [Ge]H01L 2924/01033 : Arsenic [As]H01L 2924/01041 : Niobium [Nb]H01L 2924/01042 : Molybdenum [Mo]H01L 2924/01044 : Ruthenium [Ru]H01L 2924/01045 : Rhodium [Rh]H01L 2924/01046 : Palladium [Pd]H01L 2924/01047 : Silver [Ag]H01L 2924/01049 : Indium [In]H01L 2924/0105 : Tin [Sn]H01L 2924/01051 : Antimony [Sb]H01L 2924/01056 : Barium [Ba]H01L 2924/01059 : Praseodymium [Pr]H01L 2924/01068 : Erbium [Er]H01L 2924/01072 : Hafnium [Hf]H01L 2924/01073 : Tantalum [Ta]H01L 2924/01074 : Tungsten [W]H01L 2924/01075 : Rhenium [Re]H01L 2924/01077 : Iridium [Ir]H01L 2924/01078 : Platinum [Pt]H01L 2924/01079 : Gold [Au]H01L 2924/01082 : Lead [Pb]H01L 2924/01083 : Bismuth [Bi]H01L 2924/01322 : Eutectic Alloys, i.e. obtai...H01L 2924/01327 : Intermediate phases, i.e. i...H01L 2924/014 : Solder alloysH01L 2924/04941 : TiNH01L 2924/04953 : TaNH01L 2924/05042 : Si3N4H01L 2924/0635 : Acrylic polymerH01L 2924/0665 : Epoxy resinH01L 2924/07025 : PolyimideH01L 2924/09701 : Low temperature co-fired ce...H01L 2924/10253 : Silicon [Si]H01L 2924/10329 : Gallium arsenide [GaAs]H01L 2924/12041 : LEDH01L 2924/12042 : LASERH01L 2924/1305 : Bipolar Junction Transistor...H01L 2924/13091 : Metal-Oxide-Semiconductor F...H01L 2924/14 : Integrated circuitsH01L 2924/1421 : RF devicesH01L 2924/1433 : Application-specific integr...H01L 2924/15311 : being a ball array, e.g. BGAH01L 2924/15787 : Ceramics, e.g. crystalline ...H01L 2924/15788 : Glasses, e.g. amorphous oxi...H01L 2924/181 : EncapsulationH01L 2924/19041 : being a capacitorH01L 2924/19042 : being an inductorH01L 2924/19043 : being a resistorH01L 2924/19104 : on the semiconductor or sol...H01L 2924/19105 : in a side-by-side arrangeme...H01L 2924/30105 : CapacitanceH01L 2924/3025 : Electromagnetic shielding