METHOD FOR MITIGATING IMPRINT IN A FERROELECTRIC MEMORY

• US 20100246238A1
• Filed: 03/31/2009
• Published: 09/30/2010
• Est. Priority Date: 03/31/2009
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Ramtron International Corporation (Infineon Technologies AG)
• Inventors: Taylor, Craig, Chu, Fan, Sun, Shan
• Granted Patent: US 8,081,500 B2
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit lines; and an isolation device driver for driving isolation devices coupled between the bit lines and a plurality of bit lines. The method for mitigating imprint includes coupling the bit lines to a respective plurality of sense amplifiers, turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells, disconnecting the bit lines from the respective sense amplifiers, driving the plate line low and the bit lines high, driving the plate line high and the bit lines low, driving the plate line low and floating the bit lines, driving the bit lines with the sense amplifier, and turning off the word line and precharging the bit lines. The method can be performed after each memory access, or can be performed whenever convenient with a counter and a rejuvenate command.

Claims

1. A method for mitigating imprint in an array of ferroelectric memory cells including a plurality of word lines, plate lines, and bit lines, the method comprising:

coupling the bit lines to a respective plurality of sense amplifiers;

turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells;

disconnecting the bit lines from the respective sense amplifiers;

driving the plate line low and the bit lines high;

driving the plate line high and the bit lines low;

driving the plate line low and floating the bit lines;

connecting the bit line to the sense amplifier;

driving the bit lines with the sense amplifier; and

turning off the word line and precharging the bit lines, such that the each dipole is switched at least one time.

2. The method of claim 1 further comprising using an isolation device to couple the bit lines to the sense amplifiers.

3. The method of claim 1 further comprising mitigating imprint in successive rows of the ferroelectric memory array.

4. The method of claim 1 further comprising mitigating imprint after each memory access.

5. The method of claim 1 further comprising using a rejuvenate command or pin to initiate imprint mitigation.

6. The method of claim 1 wherein a reference for each memory cell in the row is set to a voltage that is less than a switched bit line voltage and greater than an unswitched bit line voltage.

10. The method of claim 1 further comprising using a rejuvenate command or pin to initiate imprint mitigation.

11. The method of claim 1 wherein a reference for each memory cell in the row is set to a voltage that is less than a switched bit line voltage and greater than an unswitched bit line voltage.

7. A method for mitigating imprint in an array of ferroelectric memory cells including a plurality of word lines, plate lines, and bit lines, the method comprising:

periodically switching the data states of a row of memory cells in the array; and

restoring the original data states in the row of memory cells in the array.

8. The method of claim 7 further comprising mitigating imprint in successive rows of the ferroelectric memory array.

9. The method of claim 7 further comprising mitigating imprint after each memory access.

12. An array of ferroelectric memory cells that allows imprint mitigation comprising:

a plurality of ferroelectric memory cells respectively coupled to a plurality of word lines, plate lines, and bit lines;

a word line driver for driving the word lines;

a plate line driver for driving the plate lines;

a bit line driver for driving the bit lines; and

an isolation device driver for driving a plurality of isolation devices coupled to a plurality of bit lines.

13. The array of ferroelectric memory cells as in claim 12 wherein the ferroelectric capacitors change to a first polarization state

14. The array of ferroelectric memory cells as in claim 13 wherein the ferroelectric capacitors change to a second polarization state that is opposite the first polarization state.

15. The array of ferroelectric memory cells as in claim 14 wherein the memory cells comprise a second switched state.

16. The array of ferroelectric memory cells as in claim 15 wherein the memory cells comprise an original restored memory state.

17. The array of ferroelectric memory cells as in claim 13 wherein the bit lines driver comprises a high output impedance bit line driver.

18. A method for mitigating imprint in an array of ferroelectric memory cells including a plurality of word lines, plate lines, and bit lines, the method comprising:

switching a group of memory cells in the array from an original data state to a first polarization state;

store the original polarization state in the respective sense amplifiers;

switching the group of memory cells in the array from the first polarization state to a second polarization state that is opposite the first polarization state; and

switching the group of memory cells in the array from a second polarization state to a restored original data state.

19. The method of claim 18 wherein the original data state and the restored original data state comprise the same data state.

20. The method of claim 18 wherein the first data state contains only the first polarization state.

21. The method of claim 18 wherein the second data state contains only the second polarization state.

22. The method of claim 18 wherein keeping track of the ferroelectric memory cells subjected to the process comprises the use of a non-volatile counter.

23. A ferroelectric memory array comprising:

a plurality of 1T/1C ferroelectric memory cells each having a bit line node, a plate line node, and a word line node;

a plurality of sense amplifiers coupled to the bit line nodes of the memory cells through a plurality of isolation devices; and

a plurality of bit line isolation devices coupled between the bit line nodes of the memory cells.

24. The ferroelectric memory array of claim 23 wherein the plate line nodes of the memory cells are coupled together.

25. The ferroelectric memory array of claim 23 wherein the word line nodes of the memory cells are coupled together.