NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD

• US 20100246266A1
• Filed: 03/18/2010
• Published: 09/30/2010
• Est. Priority Date: 03/25/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KANG, Myoung Gon, PARK, Ki Tae
• Granted Patent: US 8,300,463 B2
• Time in Patent Office: Days
• US Class Current: 365/185.110
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks each divided into a plurality of regions, and a control logic component. The control logic component selects a memory block to be programmed based on program/erase cycles of the memory blocks, and selects a program rule used to program the regions of the selected memory block.

Claims

1. A nonvolatile memory device, comprising:

a memory cell array comprising a plurality of memory blocks respectively divided into a plurality of regions; and

a control logic component configured to select one of the memory block to be programmed based on a program or erase count of each of the respective memory blocks, and further configured to determine a program rule to be applied to the selected memory block based on program or erase counts of the respective regions of the selected memory block.

2. The nonvolatile memory device of claim 1, wherein the control logic component programs the selected memory block using a first program rule if a difference between a maximum program or erase count and a minimum program or erase count of the respective regions of the selected memory block is less than a predetermined reference value, and otherwise, the control logic component programs the selected memory block using a second program rule;

and

wherein the first program rule requires the regions of the selected memory block to be programmed in a first direction and the second program rule requires the regions of the selected memory block to be programmed in a second direction opposite the first direction.

3. The nonvolatile memory device of claim 2, wherein the first program rule causes the regions of the selected memory block to be programmed in an order beginning at a first outermost region and progressing toward a second outermost region.

4. The nonvolatile memory device of claim 1, wherein the control logic component programs the selected memory block using a first program rule if the difference between a maximum program or erase count and a minimum program or erase count of the respective regions of the selected memory block is less than a predetermined reference value, and otherwise, the control logic component programs the selected memory block using a second program rule;

and

wherein the first program rule requires the regions of the selected memory block to be programmed in a first direction starting with a first region and the second program rule requires the regions of the selected memory block to be programmed in the first direction starting with a second region different from the first region.

5. The nonvolatile memory device of claim 4, wherein the first region is an outermost region of the memory block and the second region is a non-outermost region of the memory block.

6. The nonvolatile memory device of claim 5, wherein the second region is a region that has a program or erase count close to a predetermined reference number stored in the control logic component.

7. The nonvolatile memory device of claim 4, wherein the second program rule requires the control logic component to inhibit programming of regions between the first region and the second region.

8. The nonvolatile memory device of claim 1, wherein the control logic component selects a memory block having a low program or erase count among the plurality of memory blocks and programs the selected memory block using a rule that requires the regions of the selected memory block to be programmed in an order beginning with a region having a lowest program or erase count.

9. The nonvolatile memory device of claim 1, wherein the control logic component stores a table comprising program or erase counts for the plurality of memory blocks and program or erase counts for the respective regions of the plurality of memory blocks.

10. The nonvolatile memory device of claim 1, wherein the memory cell array is a NAND flash memory cell array.

11. A method of programming a nonvolatile memory device, comprising:

selecting a memory block having a low program or erase count from a plurality of memory blocks;

selecting a program rule to be applied to the selected memory block based on information regarding program or erase counts of respective regions within the selected memory block; and

programming one of the regions of the selected memory block using the changed program rule.

12. The method of claim 11, wherein selecting the program rule comprises:

selecting a first rule as the program rule if a difference between a maximum program or erase count and a minimum program or erase count of the respective regions of the selected memory block is less than a predetermined reference value; and

otherwise, selecting a second rule as the program rule;

wherein the first rule requires the regions of the selected memory block to be programmed in a first direction and the second rule requires the regions of the selected memory block to be programmed in a second direction opposite the first direction.

13. The method of claim 11, wherein the selecting the program rules comprises:

selecting a first rule as the program rule if a difference between a maximum program or erase count and a minimum program or erase count of the respective regions of the selected memory block is less than a predetermined reference value; and

otherwise, selecting a second rule as the program rule;

wherein the first rule requires the regions of the selected memory block to be programmed in a first direction starting with a first region and the second program rule requires the regions of the selected memory block to be programmed in the first direction starting with a second region different from the first region.

14. The method of claim 13, wherein the first region is an outermost region of the memory block and the second region is a non-outermost region of the memory block.

15. The method of claim 14, wherein the second region is a region that has a program or erase count close to a predetermined reference number stored in the control logic component.

16. The method of claim 13, wherein the second rule requires the control logic component to inhibit programming of regions between the first region and the second region.