STORAGE DEVICES WITH SOFT PROCESSING

• US 20100246287A1
• Filed: 08/06/2009
• Published: 09/30/2010
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Lyric Semiconductor, Inc. (Analog Devices, Inc.)
• Inventors: Reynolds, David, Vigoda, Benjamin, Bernstein, Jeffrey, Alexeyev, Alexander, Venuti, Jeffrey
• Granted Patent: US 8,179,731 B2
• Time in Patent Office: Days
• US Class Current: 365/189.150
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Claims

1. A storage system comprising:

a first section having;

a storage array including a plurality of storage elements, each storage element operable to be written to one of a discrete set of N physical states;

a read circuit for selecting one or more storage elements and generating, for each selected storage element, an analog signal representative of the physical state of the selected storage element; and

a modulation circuit for accepting the analog signal to form a modulated representation of the analog signal from the read circuit capable of representing greater than N different states; and

a second section interfacing the first section having;

a demodulation circuit for accepting the modulated representation of the analog signal from the modulation circuit to recover the analog signal; and

a signal processing circuit for processing the recovered analog signal to generate a plurality of outputs, each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

2. The storage system of claim 1, wherein the modulation circuit is configured to form a discrete-state representation of the analog signal from the read circuit, wherein the discrete-state representation is capable of representing greater than N different states.

3. The storage system of claim 1, wherein the modulation circuit includes an analog-to-digital converter (ADC).

4. The storage system of claim 2, wherein the demodulation circuit includes a digital-to-analog converter (DAC).

5. The storage system of claim 2, wherein the ADC includes a linear ADC component.

6. The storage system of claim 2, wherein the ADC includes a non-linear ADC component.

7. The storage system of claim 1, wherein the modulated representation of the analog signal from the read circuit includes a signal of multiple quantization levels.

8. The storage system of claim 7, wherein the signal of multiple quantization levels is transmitted via a serial line to the demodulation circuit.

9. The storage system of claim 7, wherein the signal of multiple quantization levels is transmitted via multiple parallel lines to the demodulation circuit.

10. The storage system of claim 1, wherein the modulation circuit is further configured for applying a signal modulation technique to the analog signal from the read circuit to form the modulated representation of the analog signal.

11. The storage system of claim 10, wherein the signal modulation technique includes pulse-code modulation.

12. The storage system of claim 10, wherein the signal modulation technique includes pulse width modulation.

13. The storage system of claim 10, wherein the signal modulation technique includes pulse amplitude modulation.

14. The storage system of claim 10, wherein the signal modulation technique includes quadrature amplitude modulation.

15. The storage system of claim 10, wherein the signal modulation technique includes phase modulation.

16. The storage system of claim 10, wherein the signal modulation technique includes pulse-position modulation.

17. The storage system of claim 10, wherein the signal modulation technique includes stochastic modulation, and the modulated representation of the analog signal is provided as a random binary sequence of a specified probabilistic distribution.

18. The storage system of claim 1, wherein the first section is implemented as a first integrated circuit, and the second section is implemented as a second integrated circuit.

19. The storage system of claim 18, further comprising a communication link between the first and the second integrated circuits.