STORAGE DEVICES WITH SOFT PROCESSING

• US 20100246289A1
• Filed: 08/06/2009
• Published: 09/30/2010
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Lyric Semiconductor, Inc. (Analog Devices, Inc.)
• Inventors: Reynolds, David, Vigoda, Benjamin, Bernstein, Jeffrey, Alexeyev, Alexander, Venuti, Jeffrey
• Granted Patent: US 8,107,306 B2
• Time in Patent Office: Days
• US Class Current: 365/191
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Claims

1. A circuit comprising:

a signal processing circuit for accepting a discrete-valued input characterizing an observation of a signal and for generating a set of continuous-valued outputs, each output characterizing a corresponding log likelihood ratio (LLR) based measure of an association of the signal with one or more of a set of representative levels, the signal processing circuit including;

a plurality of mapping circuits, each configured to map a different range of the discrete-valued input to a respective discrete-valued output signal according to a modeling of the characteristics of the observation of the signal; and

a plurality of conversion circuits each configured for accepting the discrete-valued output signal of a corresponding mapping circuit to generate a respective one of the set of continuous-valued output.

2. The circuit of claim 1, wherein the observation of the signal includes an observation of a physical state of a selected storage element of a storage array having a plurality of storage elements.

3. The circuit of claim 2, wherein each one of the set of representative levels associated with the signal corresponds to a respective one of a set of physical states to which the storage element can be written.

4. The circuit of claim 3, further comprising a pre-processing circuit coupled to the signal processing circuit for generating the discrete-valued input of the signal processing circuit characterizing the observation of physical state of the storage element.

5. The circuit of claim 4, wherein the pre-processing circuit includes a read circuit for selecting the storage element from the plurality of storage elements to generate a discrete-valued signal representing the physical state of the selected storage element and for providing this discrete-valued signal as input to the signal processing circuit.

6. The circuit of claim 5, wherein the read circuit includes a thresholding device.

7. The circuit of claim 6, wherein the thresholding device includes a sense amplifier.

8. The circuit of claim 4, wherein the pre-processing circuit includes a read circuit for selecting the storage element from the plurality of storage elements to generate a continuous-valued signal representing the physical state of the selected storage element.

9. The circuit of claim 8, wherein the pre-processing circuit further includes an analog-to-digital converter for converting the continuous-valued signal representing the physical state of the storage element into a discrete-valued signal, and for providing this discrete-valued signal as input to the signal processing circuit.

10. The circuit of claim 3, further comprising a decoder circuit coupled to the signal processing circuit for processing the set of continuous-valued outputs of the signal processing circuit to generate a digital representation of the physical state of the storage element.

11. The circuit of claim 10, wherein the decoder circuit includes an analog decoder core configured for, in each of a plurality of cycles of a decoding operation, accepting a portion of code data and a portion of an intermediate value date to generate an output.

12. The circuit of claim 11, wherein the decoder circuit further includes an analog storage for storing the output of the analog decoder core.

13. The circuit of claim 11, wherein the portion of code data accepted in each of the plurality of cycles of the decoding operation includes data representing the physical state of each of a subset of two or more storage elements selected from the storage array.

14. The circuit of claim 1, wherein the modeling of the characteristics of the observation of the signal includes a modeling of an expected degree of variability in the observation of the signal.

15. The circuit of claim 1, wherein each one of the plurality of mapping circuits forms a substantially piece-wise linear mapping of the different range of the discrete-valued input to the respective discrete-valued output signals.

16. The circuit of claim 1, wherein each mapping circuit includes a look-up table.

17. The circuit of claim 1, wherein each mapping circuit includes one or more logic gates.

18. The circuit of claim 1, wherein each conversion circuit includes a digital-to-analog converter.