METHOD AND APPARATUS FOR GATE TRAINING IN MEMORY INTERFACES

• US 20100246290A1
• Filed: 03/30/2009
• Published: 09/30/2010
• Est. Priority Date: 03/30/2009
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Denali Software Incorporated (Cadence Group)
• Inventors: MacLaren, John, Espinoza, Anne
• Granted Patent: US 8,098,535 B2
• Time in Patent Office: Days
• US Class Current: 365/193
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

An invention is provided for gate training in memory interfaces. The invention includes adding a coarse delay to a gate assert time, where the coarse delay is a predefined period of time and the gate assert time is a time when a data strobe gate signal is asserted. Next, the a data strobe signal is repeatedly sampled at the gate assert time until a rising edge of the data strobe signal is found, wherein a fine delay is added to the gate assert time between sampling of the data strobe signal. The fine delay is a period of time shorter than the coarse delay. Once the rising edge is found, the coarse delay is removed from the gate assert time, thus setting the gate assert time centrally within the preamble of the data strobe signal.

Claims

1. A method for gate training in a memory interface, comprising the operations of:

adding a coarse delay to a gate assert time, wherein the coarse delay is a predefined period of time, and wherein the gate assert time is a time when a data strobe gate signal is asserted;

repeatedly sampling a data strobe signal at the gate assert time until a rising edge of the data strobe signal is found, wherein a fine delay is added to the gate assert time between sampling of the data strobe signal, the fine delay being a period of time shorter than the coarse delay; and

removing the coarse delay from the gate assert time.

2. A method as recited in claim 1, wherein the coarse delay is one half a clock period.

3. A method as recited in claim 1, wherein the fine delay is less than one quarter of a clock period.

4. A method as recited in claim 1, further comprising the operations of

obtaining an initial data strobe sample by sampling the data strobe signal at the gate assert time after adding the coarse delay to the gate assert time;

and

removing an additional full clock period from the gate assert time when the initial data strobe sample is HIGH.

5. A method as recited in claim 4, wherein the initial data strobe sample is sampled during a time period defined by a beginning of a preamble period of the data strobe signal and a first falling edge of the data strobe signal.

6. A method as recited in claim 1, wherein the data strobe is sampled using a register receiving the data strobe signal as input and utilizing the data strobe gate signal as a clock source.

7. A method as recited in claim 1, wherein the coarse delay is obtained by asserting the data strobe gate signal based on a falling edge of an internal clock source.

8. A method as recited in claim 1, wherein the coarse delay is obtained by incrementing the gate assert time by a predefined number of delay elements, wherein each delay element is of a period of time shorter than the coarse delay.

9. A method for gate training in a memory interface, comprising the operations of:

adding a coarse delay to a gate assert time, wherein the coarse delay is a predefined period of time, and wherein the gate assert time is a time when a data strobe gate signal is asserted;

repeatedly sampling a data strobe signal at the gate assert time until a rising edge of the data strobe signal is found, wherein a fine delay is added to the gate assert time between sampling of the data strobe signal, the fine delay being a period of time shorter than the coarse delay;

removing the coarse delay from the gate assert time; and

performing a preamble check by sampling the data strobe signal at a time based on the gate assert time to determine whether the gate assert time is within a preamble of the data strobe signal.

10. A method as recited in claim 9, further comprising the operation of removing a full clock period from the gate assert time when the gate assert time is outside the preamble during the preamble check.

11. A method as recited in claim 9, wherein the coarse delay is one half a clock period.

12. A method as recited in claim 9, wherein the fine delay is less than one quarter of a clock period.

13. A method as recited in claim 9, wherein the coarse delay is obtained by asserting the data strobe gate signal based on a falling edge of an internal clock source.

14. A method as recited in claim 9, wherein the coarse delay is obtained by incrementing the gate assert time by a predefined number of delay elements, wherein each delay element is of a period of time shorter than the coarse delay.

15. A method as recited in claim 9, wherein a write leveling delay is added to the gate assert time in addition to the coarse delay and fine delay are added to the gate assert time.

16. A circuit for gate training in a memory interface, comprising:

logic that adds a coarse delay to a gate assert time, wherein the coarse delay is a predefined period of time, and wherein the gate assert time is a time when a data strobe gate signal is asserted;

logic that repeatedly sampling a data strobe signal at the gate assert time until a rising edge of the data strobe signal is found, wherein a fine delay is added to the gate assert time between sampling of the data strobe signal, the fine delay being a period of time shorter than the coarse delay; and

logic that removes the coarse delay from the gate assert time.

17. A circuit as recited in claim 16, wherein the coarse delay is one half a clock period.

18. A circuit as recited in claim 16, wherein the fine delay is less than one quarter of a clock period.

19. A circuit as recited in claim 16, further comprising logic that performs a preamble check by sampling the data strobe signal at a time based on the gate assert time to determine whether the gate assert time is within a preamble of the data strobe signal.

20. A circuit as recited in claim 19, further comprising logic that removes a full clock period from the gate assert time when the gate assert time is outside the preamble during the preamble check.