SYSTEM ARCHITECTURE FOR VERY FAST ETHERNET BLADE
First Claim
1. A system to provide data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices, the system comprising:
- a media access control (MAC) interface to facilitate receipt and transmission of packets over a physical interface;
a first processor coupled to the MAC interface to receive packets from the MAC interface and to perform initial processing of packets, and further to dispatch packets to a first memory;
a second processor to retrieve packets from the first memory and to compute an appropriate destination, and further to dispatch packets to a backplane;
a third processor to receive packets from the backplane and to organize the packets for transmission, and further to dispatch packets to a second memory; and
a fourth processor coupled to the MAC interface and to retrieve packets from the second memory and to schedule the transmission of packets to the MAC interface for transmission to one or more destination devices.
1 Assignment
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Accused Products
Abstract
The system of the present invention provides data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. The system comprises a media access control (MAC) interface to facilitate receipt and transmission of packets over a physical interface. A first field programmable gate array is coupled to the MAC interface and operative to receive packets from the MAC interface and configured to perform initial processing of packets, which are dispatched to a first memory. A second field programmable gate array is operative to retrieve packets from the first memory and configured to compute an appropriate destination, which is used to dispatch packets to a backplane. A third field programmable gate array is provided that is operative to receive packets from the backplane and configured to organize the packets for transmission, which are dispatched to a second memory. A fourth field programmable gate array is coupled to the MAC interface and operative to retrieve packets from the second memory and configured to schedule the transmission of packets to the MAC interface for transmission to one or more destination devices.
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Citations
20 Claims
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1. A system to provide data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices, the system comprising:
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a media access control (MAC) interface to facilitate receipt and transmission of packets over a physical interface; a first processor coupled to the MAC interface to receive packets from the MAC interface and to perform initial processing of packets, and further to dispatch packets to a first memory; a second processor to retrieve packets from the first memory and to compute an appropriate destination, and further to dispatch packets to a backplane; a third processor to receive packets from the backplane and to organize the packets for transmission, and further to dispatch packets to a second memory; and a fourth processor coupled to the MAC interface and to retrieve packets from the second memory and to schedule the transmission of packets to the MAC interface for transmission to one or more destination devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification