SIGNAL-POWERED INTEGRATED CIRCUIT WITH ESD PROTECTION

• US 20100246695A1
• Filed: 06/07/2010
• Published: 09/30/2010
• Est. Priority Date: 06/23/2005
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Bark, Boris A., Yoder, James D., Kiss, Peter, Ransijn, Johannes G., Grande, Brad L.
• Granted Patent: US 8,867,182 B2
• Time in Patent Office: Days
• US Class Current: 375/257
• CPC Class Codes: H04M 19/001 Current supply source at the exchanger providing current to substations

Abstract

The invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal'"'"'s predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse.

Claims

1. A signal-powered integrated circuit, comprising:

an integrated circuit die including a ground node, a supply node, and a first terminal for receiving an digital data signal having a predetermined energy;

a receive buffer formed on the integrated circuit die, connected to the first terminal and capable of receiving the data associated with the digital data signal; and

a rectifier formed on the integrated circuit die, the rectifier including

a first diode connected between the first terminal and the ground node, and

a second diode connected between the first terminal and the supply node,

wherein the rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal'"'"'s predetermined energy to the supply node,

wherein each of the first and second diodes is capable of withstanding an electrostatic discharge (ESD) impulse.

2. The circuit of claim 1, wherein each diode in the rectifier is capable of withstanding an ESD impulse of at least about 1000 volts.

3. The circuit of claim 2, wherein each diode in the rectifier is capable of withstanding an ESD impulse in the range from about 1000 volts to about 2000 volts.

4. The circuit of claim 1, wherein the first and second diodes are parasitic diodes in a first transistor and a second transistor, respectively.

5. The circuit of claim 1, wherein the average energy of the digital data signal is sufficiently large to cause the first and second diodes to operate as a rectifier.

6. The circuit of claim 1, wherein the first and second diodes are the primary devices or the only devices that protect the integrated circuit die from electrostatic discharge through the first terminal.

7. The circuit of claim 1, wherein

the digital data signal is a differential signal formed by a first signal and a second signal complementary to the first, and wherein the first terminal is capable of receiving the first signal;

the integrated circuit die further includes a second terminal capable of receiving the second signal; and

the rectifier further includes

a third diode connected between the second terminal and the ground node, and

a fourth diode connected between the second terminal and the supply node;

wherein the first, second, third and fourth diodes together provide full-wave rectification for the differential input signal, and

wherein each of the third and fourth diodes is capable of withstanding an ESD impulse.

8. A method of powering an integrated circuit, comprising the steps of:

receiving a first digital data signal having data content and a predetermined energy at a first terminal of the integrated circuit;

rectifying a portion of the first digital data signal via a first diode connected between the first terminal and a ground node of the integrated circuit, and a second diode connected between the first terminal and a supply node of the integrated circuit; and

storing at least a portion of the first digital data signal'"'"'s predetermined energy at the supply node;

wherein each of the first and second diodes is capable of withstanding an ESD impulse.

9. The circuit of claim 8, wherein each diode in the rectifier is capable of withstanding an ESD impulse of at least about 1000 volts.

10. The circuit of claim 8, wherein each diode in the rectifier is capable of withstanding an ESD impulse in the range from about 1000 volts to about 2000 volts.

11. The method of claim 8, wherein the first and second diodes are parasitic diodes in a first transistor and a second transistor, respectively.

12. The method of claim 8, wherein

the first digital data signal has an average energy that is sufficiently large to enable the rectifier to rectify the digital data signal.

13. The method of claim 8, further comprising the step of protecting the integrated circuit from electrostatic discharge through the first terminal by the first and second diodes.

14. The method of claim 8, further comprising the step of buffering the data content associated with the first digital data signal.

15. The method of claim 8, further comprising the steps of:

receiving a second digital data signal having data content and a predetermined energy at a second terminal of the integrated circuit, the second digital data signal forming a differential signal with the first digital data signal;

buffering the data content associated with the second digital data signal;

rectifying a portion of the second digital data signal via a third diode connected between the second terminal and the ground node of the integrated circuit, and a fourth diode connected between the second terminal and the supply node of the integrated circuit, each diode being capable of withstanding an ESD impulse; and

storing at least a portion of the second digital data signal'"'"'s predetermined energy at the supply node; and

thereby full-wave rectifying the differential signal.