INTER-PROCESSOR COMMUNICATION LINK WITH MANAGEABILITY PORT

• US 20100250821A1
• Filed: 06/08/2010
• Published: 09/30/2010
• Est. Priority Date: 03/29/2004
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: MUELLER, Peter D.
• Granted Patent: US 8,601,145 B2
• Time in Patent Office: Days
• US Class Current: 710/313
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0742 in a data processing system embedded in a mobile device, e.g. mobile phones, handheld devices
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Manageability ports for inter-processor communication links, along with associated systems and methods, are generally provided.

Claims

1. A management port for a wireless device platform, comprising:

a communication link having a physical link, local to a microprocessor subsystem, to be used in inter-processor communication over an inter-processor bus for the wireless device platform, the communication link to provide an inbound link and an outbound link,

the inbound link providing a path for communications from the inter-processor bus to a peripheral bus of the microprocessor subsystem, the inbound link receiving communications from at least one processor or peripheral communicating over the inter-processor bus,

the outbound link providing a path for communications from the peripheral bus of the microprocessor subsystem to the inter-processor bus, the outbound link transmitting communications over the inter-processor bus to the at least one processor or peripheral, and

the communication link to control data flow over the inbound and outbound links, the microprocessor subsystem comprising a processor core, at least one processor subsystem, and a microprocessor bus system, the microprocessor bus system providing a communication path between the processor core and the at least one processor subsystem; and

a management block to receive command data from the at least one processor or peripheral through a predetermined logic channel in the inbound link, the management block providing a corresponding command signal on the microprocessor bus system, which relays the command signal to at least one processor or peripheral of the microprocessor subsystem, the command signal performing a management function for the microprocessor subsystem, the management block being further adapted to receive a response signal from the microprocessor bus system and the management block transmitting corresponding response data through a predetermined logic channel in the outbound link to the at least one processor or peripheral via the inter-processor bus, the management block including a manageability control module,

the manageability control module configured to apply a protocol for communicating over the microprocessor bus system, and

the manageability control module configured to provide access for allowing another microprocessor subsystem to perform the management function even when the processor core is not responsive to any signal.